## Multi-Panel Figure: Memristor Circuit and Characterization ### Overview The image presents a multi-panel figure detailing a memristor-based circuit, its characterization, and performance. The figure includes a schematic diagram of the circuit, a photograph of the experimental setup, cumulative distribution functions (CDFs) of conductance, voltage waveforms, and a conductance heatmap. ### Components/Axes **Panel a:** * **Labels:** `<N>`, `<W>`, `<S>`, `<E>` are placed above a schematic of a memristor array. * The array consists of two rows of memristors, some filled in dark green, some light green, and some white. * The array is enclosed in a light blue box. **Panel b:** * **Labels:** V_bot, V_in<0>, V_in<1>, V_in<N>, V_top, V_x, i_in, i_buff, i_ref, V_out, G₀, G₁, G_N. * The panel shows a circuit diagram with memristors connected to an amplifier and other circuit elements. * Microscope images of the device are shown as insets. **Panel c:** * A photograph of the experimental setup, including a microscope and associated electronics. **Panel d:** * **Axes:** * X-axis: Conductance (µS), ranging from 0 to 125. * Y-axis: CDF, ranging from 0.0 to 1.0. * **Labels:** "Threshold" (vertical dashed red line at approximately 60 µS), "LCS" (light green curve), "HCS" (dark green curve). **Panel e:** * **Axes:** * X-axis: Time (µs), ranging from -4 to 8. * Y-axis: Voltage (V), ranging from 0.0 to 1.2. * **Labels:** V_in<N> (blue dashed line), V_in<S> (red dashed-dotted line), V_out<E> (solid black line). **Panel f:** * **Axes:** * X-axis: Inputs, labeled 0, 1, 2, 3. * Y-axis: Outputs, labeled 0, 1. * Vertical Colorbar: Conductance (µS), ranging from 0 to 100. * The panel shows a 2x4 heatmap with varying shades of green, representing conductance values. ### Detailed Analysis **Panel d (CDF Plot):** * **LCS (Light Green):** The CDF of the LCS (Low Conductance State) starts at 0 and rises sharply, reaching 1.0 around 50 µS. * **HCS (Dark Green):** The CDF of the HCS (High Conductance State) starts at 0 and rises more gradually, reaching approximately 0.3 at 125 µS. * **Threshold:** The vertical red dashed line indicates a threshold value of approximately 60 µS. **Panel e (Voltage Waveforms):** * **V_in<N> (Blue Dashed):** The input voltage at node N switches between approximately 0 V and 1.2 V. * **V_in<S> (Red Dashed-Dotted):** The input voltage at node S switches between approximately 0 V and 1.2 V, with a slight delay compared to V_in<N>. * **V_out<E> (Solid Black):** The output voltage at node E switches between approximately 0 V and 1.2 V, responding to the input voltages. **Panel f (Conductance Heatmap):** * The heatmap represents the conductance values for different input and output combinations. * The conductance values range from approximately 20 µS (lightest green) to 80 µS (darkest green). * Specific conductance values for each input/output combination: * Output 0: * Input 0: ~80 µS * Input 1: ~20 µS * Input 2: ~80 µS * Input 3: ~20 µS * Output 1: * Input 0: ~20 µS * Input 1: ~80 µS * Input 2: ~20 µS * Input 3: ~80 µS ### Key Observations * The CDF plot (Panel d) shows a clear separation between the low and high conductance states of the memristor. * The voltage waveforms (Panel e) demonstrate the switching behavior of the memristor circuit in response to input signals. * The conductance heatmap (Panel f) indicates that the memristor array can perform logic operations based on the input signals. ### Interpretation The data presented in the figure demonstrates the functionality of a memristor-based circuit. The CDF plot confirms the existence of distinct conductance states, which are essential for memristor-based memory and logic applications. The voltage waveforms show the dynamic response of the circuit to input signals, indicating its ability to perform switching operations. The conductance heatmap illustrates the potential of the memristor array for implementing logic functions, where different input combinations result in distinct output conductance values. The arrangement of the memristors and the circuit design enable the implementation of logic gates or other computational functions. The experimental setup photograph provides context for the physical implementation of the circuit.

## Diagram Set: Neuromorphic Computing Components & Characteristics ### Overview This image presents a set of diagrams and data visualizations related to neuromorphic computing, specifically focusing on memristive devices and their application in building logic gates and neural networks. The image is divided into six sections (a-f), each illustrating a different aspect of the system. ### Components/Axes * **a:** Schematic representation of a memristive crossbar array with labeled inputs: <N>, <W>, <S>, <E>. * **b:** Circuit diagram showing the implementation of a logic gate using memristors and an operational amplifier. Includes transistor schematics and voltage labels (V_bot, V_in, V_buff, V_out). * **c:** Photograph of a physical experimental setup, likely a probe station with a memristive device under test. * **d:** Cumulative Distribution Function (CDF) plot of conductance (µS) with labeled curves: LCS (Low Conductance State) and HCS (High Conductance State). X-axis: Conductance (µS) from 0 to 125. Y-axis: CDF from 0 to 1.0. A vertical line indicates a "Threshold" value at approximately 25 µS. * **e:** Time-series plot of voltage (V_in) vs. time (µs) for different input signals: V_in <N>, V_in <W>, V_in <S>, V_in <E>. X-axis: Time (µs) from -4 to 8. Y-axis: Voltage (V) from 0 to 1.2. * **f:** Heatmap showing conductance (µS) as a function of inputs (0, 1, 2, 3) and outputs. X-axis: Inputs (0, 1, 2, 3). Y-axis: Conductance (µS) from 20 to 80. ### Detailed Analysis or Content Details **a:** The schematic shows a grid of square elements, presumably memristors, arranged in a crossbar configuration. The inputs <N>, <W>, <S>, and <E> likely represent North, West, South, and East, indicating the direction of addressing or signal input. **b:** The circuit diagram illustrates a differential amplifier configuration. The memristors (labeled G_i) are connected in series between the input and output. The transistors are arranged in a cascaded inverter configuration. The diagram shows how the memristor's conductance modulates the output voltage. **c:** The photograph shows a complex experimental setup with various cables and components. It appears to be a probe station used for making electrical contact with a small device. **d:** The CDF plot shows the distribution of conductance values for the memristive devices. The LCS curve rises steeply from 0 to approximately 0.4 at around 10 µS, indicating a high probability of low conductance states. The HCS curve rises more gradually, reaching 0.4 at around 50 µS, indicating a broader distribution of high conductance states. The threshold is set at approximately 25 µS. **e:** The time-series plot shows voltage pulses for each input signal. The pulses are approximately 2 µs wide and have a peak voltage of around 1.2 V. The pulses are offset in time, suggesting sequential application of inputs. **f:** The heatmap shows the relationship between inputs and conductance. The color intensity represents the conductance value. The heatmap appears to demonstrate a non-linear relationship between inputs and outputs, with varying conductance values for different input combinations. The conductance values range from approximately 20 µS to 80 µS. The pattern suggests a complex mapping between inputs and outputs, potentially representing a logic function or a neural network weight matrix. ### Key Observations * The CDF plot (d) shows a clear bimodal distribution of conductance, indicating distinct low and high conductance states. * The time-series plot (e) demonstrates the ability to apply different input signals sequentially. * The heatmap (f) suggests a complex, non-linear relationship between inputs and outputs, indicative of computational functionality. * The circuit diagram (b) shows a potential implementation of a logic gate using memristors. ### Interpretation The image demonstrates the potential of memristive devices for building neuromorphic computing systems. The crossbar array (a) provides a dense connectivity matrix, while the circuit diagram (b) shows how memristors can be used to implement logic gates. The CDF plot (d) confirms the bistable nature of the memristors, allowing them to store information in the form of conductance states. The time-series plot (e) shows the ability to control the input signals, and the heatmap (f) suggests that the system can perform complex computations. The threshold value in the CDF plot (d) is crucial for defining the switching behavior of the memristors. The non-linear relationship between inputs and outputs in the heatmap (f) is a key characteristic of neural networks and other complex computational systems. The experimental setup in (c) suggests that these concepts are being actively investigated in a laboratory setting. The overall data suggests a functional neuromorphic system capable of performing computations based on the manipulation of memristive conductance states. The system's ability to represent and process information in a manner analogous to the human brain could lead to significant advances in artificial intelligence and machine learning.

## Diagram: Multi-Stage Signal Processing System ### Overview The image depicts a multi-stage technical system combining directional input processing, electronic circuitry, and data visualization. It includes: - A grid-based input matrix (a) - A signal conditioning circuit (b) - Experimental hardware (c) - Conductance distribution functions (d) - Time-voltage response traces (e) - Input-output heatmap (f) ### Components/Axes #### a. Directional Input Grid - Labels: `<N>`, `<W>`, `<S>`, `<E>` (cardinal directions) - Structure: 2x4 grid of green squares with blue boundary highlighting active regions #### b. Signal Conditioning Circuit - Components: - Voltage sources: `V_in`, `V_top`, `V_bot` - Gain stages: `G1`, `G2` - Buffer: `V_buff` - Output: `V_out` - Flow: Input signals pass through gain stages, buffered, and outputted #### c. Experimental Setup - Microscope with attached electronics - Wiring harness connecting to signal processing unit #### d. Conductance Distribution Function (CDF) - Axes: - x-axis: Conductance (μS) from 0 to 125 - y-axis: CDF (0 to 1) - Threshold line: Vertical red line at ~75 μS - Regions: - LCS (Low Conductance State): Left of threshold - HCS (High Conductance State): Right of threshold #### e. Time-Voltage Response - Axes: - x-axis: Time (μs) from 0 to 6 - y-axis: Voltage (V) from -4 to 1.2 - Traces: - `V_in` (blue): Sharp spikes at 1.5μs, 3.5μs, 5.5μs - `V_N` (dashed blue): Stable at ~0.2V - `V_S` (orange): Peaks at 2.5μs, 4.5μs - `V_E` (red): Peaks at 1.5μs, 3.5μs, 5.5μs #### f. Input-Output Heatmap - Axes: - x-axis: Inputs (0-3) - y-axis: Outputs (0-1) - Color coding: - Green: Active (1) - White: Inactive (0) - Pattern: Diagonal green blocks suggesting input-output correlation ### Detailed Analysis 1. **Directional Input Processing (a)**: - Grid structure suggests spatial encoding of directional stimuli - Blue boundary highlights active quadrants (likely N/S or W/E pairs) 2. **Circuit Functionality (b)**: - Gain stages (`G1`, `G2`) amplify input signals - Buffer stage isolates output from load variations - Voltage references (`V_top`, `V_bot`) define operational range 3. **Experimental Validation (c)**: - Microscope setup implies optical input to the system - Wiring complexity suggests multi-channel data acquisition 4. **Conductance Thresholding (d)**: - LCS/HCS demarcation at ~75 μS - CDF curve shows 80% of samples below threshold 5. **Dynamic Response (e)**: - `V_in` exhibits periodic spiking matching input stimuli - `V_E` (red) shows strongest correlation with input timing - All traces stabilize after 6μs 6. **Input-Output Mapping (f)**: - 4x2 matrix shows deterministic relationships - Output 1 activates for inputs 0-2 - Output 0 activates for input 3 ### Key Observations - **Temporal Synchronization**: Voltage spikes in (e) align with input activation times - **Threshold Sensitivity**: 75 μS cutoff separates LCS/HCS with 80% CDF coverage - **Circuit Gain**: `V_out` amplitude (~1.2V) exceeds input range (~0.4V) - **Heatmap Symmetry**: Diagonal pattern suggests input-output parity ### Interpretation This system implements a directional sensing mechanism where: 1. Spatial inputs (`<N>`, `<W>`, etc.) are converted to electrical signals 2. Gain stages amplify signals to overcome noise 3. Conductance thresholding enables binary state classification (LCS/HCS) 4. Time-varying voltage responses validate input-output timing relationships 5. Heatmap confirms input-output mapping rules The LCS/HCS threshold at 75 μS likely represents a critical conductance level for state transition. The 80% CDF below threshold suggests the system spends most time in LCS, with HCS reserved for high-confidence inputs. The voltage response traces demonstrate the system's ability to track rapid input changes (spike timing precision <1μs). The heatmap's diagonal pattern indicates a 1:1 input-output relationship for most cases, with input 3 acting as a special case (always 0 output). The experimental setup (c) suggests this is a proof-of-concept for neuromorphic computing or tactile sensing systems, where directional inputs trigger state changes monitored through conductance measurements. The buffer stage (b) ensures signal integrity during high-gain amplification, critical for maintaining response fidelity in noisy environments.