## Diagram: Layered Architecture ### Overview The image depicts a layered architecture diagram, showing the flow of data and processes through three distinct layers: Kernel Layer (L1), Wrapper Layer (L2), and Class Layer (L3). Each layer contains "Subgraph-based" and "Graph-based" components. The diagram illustrates how customized layers are built upon lower-level kernels and runtime environments. ### Components/Axes * **Layers:** * L1: Kernel Layer * L2: Wrapper Layer * L3: Class Layer * **Components within each layer:** * Subgraph-based * Graph-based * **Additional Elements:** * "Forward_fpga" (appears in Class Layer) * "AOCX" (appears in Kernel Layer) * **Arrows:** Blue arrows indicate the flow of data/processes from the Class Layer to the Wrapper Layer and then to the Kernel Layer. ### Detailed Analysis * **L1: Kernel Layer:** * Contains "Subgraph-based Kernels" and "Graph-based Kernels." * Labeled as "AOCX" at the bottom. * **L2: Wrapper Layer:** * Contains "Subgraph-based Runtime" and "Graph-based Runtime." * **L3: Class Layer:** * Contains "Customized Layer Subgraph-based" and "Customized Layer Graph-based." * Each of these components has a yellow box labeled "Forward_fpga." * **Flow:** * The flow is top-down, from L3 to L1, indicated by blue arrows. ### Key Observations * The architecture is structured in a layered fashion, with each layer building upon the previous one. * Both "Subgraph-based" and "Graph-based" components are present in each layer, suggesting parallel processing or different approaches to the same task. * The "Forward_fpga" component in the Class Layer likely represents a forward pass operation on an FPGA. * "AOCX" at the Kernel Layer might indicate a specific hardware or software platform. ### Interpretation The diagram illustrates a hierarchical system where high-level customized layers (L3) rely on lower-level runtime environments (L2) and fundamental kernels (L1). The presence of both "Subgraph-based" and "Graph-based" components suggests a hybrid approach to processing, possibly leveraging the strengths of both methods. The "Forward_fpga" component indicates hardware acceleration using FPGAs. The "AOCX" label at the Kernel Layer likely refers to a specific hardware or software platform upon which the entire architecture is built. The diagram suggests a modular and flexible design, allowing for customization and optimization at different levels of the system.

\n ## Diagram: AOCX Layer Architecture ### Overview The image depicts a layered architecture diagram for a system named "AOCX". It illustrates the flow of data and processing through three layers: L1 (Kernel Layer), L2 (Wrapper Layer), and L3 (Class Layer). Each layer contains two parallel processing paths: one "Subgraph-based" and one "Graph-based". The diagram emphasizes the interaction between these paths at each layer. ### Components/Axes The diagram is structured into three main layers, labeled on the right side: * **L3: Class Layer** * **L2: Wrapper Layer** * **L1: Kernel Layer** Within each layer, there are two blocks: * **Subgraph-based** * **Graph-based** Arrows indicate the flow of data from the top layers (L3) down to the bottom layer (L1). Each block in the Class Layer contains the text "Forward_fpga". The bottom layer is labeled "AOCX". ### Detailed Analysis or Content Details The diagram shows a parallel processing structure. * **L3 (Class Layer):** Contains two blocks, positioned horizontally. * Left Block: "Customized Layer Subgraph-based" with "Forward_fpga" inside. * Right Block: "Customized Layer Graph-based" with "Forward_fpga" inside. * Dotted arrows originate from both blocks, pointing downwards. * **L2 (Wrapper Layer):** Contains two blocks, positioned horizontally, directly below the L3 blocks. * Left Block: "Subgraph-based Runtime" * Right Block: "Graph-based Runtime" * Solid arrows originate from the corresponding blocks in L3 and point downwards to the L2 blocks. * **L1 (Kernel Layer):** Contains two blocks, positioned horizontally, directly below the L2 blocks. * Left Block: "Subgraph-based Kernels" * Right Block: "Graph-based Kernels" * Solid arrows originate from the corresponding blocks in L2 and point downwards to the L1 blocks. * The entire L1 layer is contained within a rectangular box labeled "AOCX". The arrows indicate a unidirectional flow of data from the Class Layer (L3) through the Wrapper Layer (L2) to the Kernel Layer (L1). The "Forward_fpga" text suggests a forward pass operation implemented on an FPGA. ### Key Observations The diagram highlights a dual-path architecture, with both subgraph-based and graph-based processing occurring in parallel at each layer. The "Forward_fpga" label suggests that the forward pass is optimized for FPGA implementation. The AOCX label at the bottom indicates that the entire system is encapsulated within this framework. ### Interpretation This diagram likely represents the architecture of a hardware acceleration system, specifically designed for deep learning or graph processing. The separation into layers (Class, Wrapper, Kernel) suggests a modular design, where each layer performs a specific function. The parallel subgraph-based and graph-based paths indicate that the system can leverage different processing strategies simultaneously, potentially improving performance and flexibility. The "Forward_fpga" label strongly suggests that the system is intended to be deployed on an FPGA, taking advantage of its parallel processing capabilities. The AOCX label likely refers to a specific hardware or software framework used to manage and optimize the system. The diagram demonstrates a clear flow of data from a high-level customized layer down to the low-level kernel implementation, optimized for FPGA execution.

## System Architecture Diagram: Layered Processing Model ### Overview The image displays a technical architecture diagram illustrating a three-layered system for processing computational tasks, specifically distinguishing between "Subgraph-based" and "Graph-based" approaches. The diagram shows a top-down flow of data or control from a high-level class layer, through a wrapper/runtime layer, to a low-level kernel layer. The overall system is labeled "AOCX" at the bottom. ### Components/Layers The diagram is organized into three horizontal layers, labeled on the right side: 1. **L3: Class Layer** (Top) * Contains two primary components: * `Customized Layer Subgraph-based` * `Customized Layer Graph-based` * Each of these components contains a yellow-highlighted sub-component labeled `Forward_Tags`. 2. **L2: Wrapper Layer** (Middle) * Contains two runtime components: * `Subgraph-based Runtime` * `Graph-based Runtime` * These are connected to the L3 components above by downward-pointing blue arrows. 3. **L1: Kernel Layer** (Bottom) * Contains two kernel components: * `Subgraph-based Kernels` * `Graph-based Kernels` * These are connected to the L2 components above by downward-pointing blue arrows. * The entire L1 layer is enclosed in a dashed box labeled `AOCX` at the bottom. **Additional Text Elements:** * Ellipses (`......`) appear to the left of the L3 components and below the L1 layer, suggesting the diagram is part of a larger or extensible system. * The text "L3: Class Layer", "L2: Wrapper Layer", and "L1: Kernel Layer" are positioned to the right of their respective layers. ### Detailed Analysis The diagram defines a clear, parallel processing pipeline with two distinct paths: * **Path 1 (Left):** `Customized Layer Subgraph-based` (L3) → `Subgraph-based Runtime` (L2) → `Subgraph-based Kernels` (L1). * **Path 2 (Right):** `Customized Layer Graph-based` (L3) → `Graph-based Runtime` (L2) → `Graph-based Kernels` (L1). The `Forward_Tags` component within each L3 class layer is highlighted in yellow, indicating it is a key functional unit or data structure passed down the pipeline. The blue arrows consistently point downward, indicating a unidirectional flow of information or command from the higher abstraction layer (Class) to the lower execution layer (Kernel). ### Key Observations 1. **Symmetrical Design:** The architecture is perfectly symmetrical, with identical structural layers for both the Subgraph-based and Graph-based processing paradigms. 2. **Clear Separation of Concerns:** Each layer has a distinct responsibility: L3 for high-level customization/class definition, L2 for runtime management/wrapping, and L1 for low-level kernel execution. 3. **Unified Lower Layer:** Both processing paths converge into the single `AOCX` system at the Kernel Layer (L1), suggesting a common underlying execution framework or hardware abstraction. 4. **Forward_Tags Emphasis:** The yellow highlighting on `Forward_Tags` in the Class Layer suggests this is a critical data packet or metadata container that initiates the processing flow. ### Interpretation This diagram represents a **modular, dual-pathway computational framework** designed to handle both subgraph-level and graph-level operations. The architecture prioritizes abstraction and separation of concerns. * **What it demonstrates:** The system is built to support two complementary computational models (subgraph and graph) through a clean, layered interface. This allows for specialized optimization at each level (class, runtime, kernel) while maintaining a unified backend (`AOCX`). * **Relationships:** The vertical relationships are hierarchical (abstraction to execution). The horizontal relationship between the Subgraph and Graph paths is one of parallel specialization; they are alternative or complementary methods processed by the same layered infrastructure. * **Notable Design Choice:** The encapsulation of `Forward_Tags` within the Class Layer implies that the initial processing directive or data context is defined at the highest level and propagated downward, ensuring each subsequent layer has the necessary metadata to perform its function correctly. The ellipses (`......`) indicate this is a scalable or extensible pattern, not a closed system. **Language Note:** All text in the image is in English.

## Diagram: Layered Architecture for Subgraph/Graph-based Processing ### Overview The diagram illustrates a three-layered computational architecture for processing subgraph- and graph-based data. It shows a hierarchical flow from kernel-level operations to specialized customization layers, culminating in a class layer. The architecture emphasizes FPGA acceleration ("AOCX") and runtime optimization. ### Components/Axes 1. **L1: Kernel Layer** - Contains two kernel types: - Subgraph-based Kernels - Graph-based Kernels - Outputs to AOCX (Xilinx FPGA acceleration framework) 2. **L2: Wrapper Layer** - Contains two runtime modules: - Subgraph-based Runtime - Graph-based Runtime - Receives input from L1 kernels - Feeds into L3 customization layers 3. **L3: Class Layer** - Contains two customized processing units: - Customized Layer Subgraph-based - Customized Layer Graph-based - Both connect to a shared "forward_fpga" block - Positioned at the top of the hierarchy ### Spatial Relationships - Vertical hierarchy: L1 (bottom) → L2 (middle) → L3 (top) - Horizontal parallelism within each layer: - Subgraph-based components on left - Graph-based components on right - Arrows indicate data flow direction (bottom-up) - "forward_fpga" block acts as terminal output node ### Key Observations 1. **Dual Processing Paths**: Both subgraph and graph-based implementations maintain parallel processing streams throughout all layers 2. **FPGA Integration**: AOCX framework appears as foundational infrastructure connecting kernel outputs 3. **Customization Focus**: L3 emphasizes specialized processing through "Customized Layer" components 4. **Runtime Optimization**: L2 explicitly separates runtime management from kernel execution ### Interpretation This architecture represents a specialized machine learning or graph processing system optimized for FPGA deployment. The three-layer structure suggests: 1. **Kernel Layer (L1)**: Basic computational units handling raw data/graph operations 2. **Wrapper Layer (L2)**: Middleware managing execution context and resource allocation 3. **Class Layer (L3)**: Application-specific customization enabling domain adaptation The shared "forward_fpga" block indicates a unified acceleration path for both processing paradigms, suggesting hardware-software co-design optimization. The parallel subgraph/graph implementation implies support for heterogeneous graph data types while maintaining computational efficiency through FPGA acceleration.