## System Architecture Diagram: Arria 10 SoC FPGA with HPS and CNN Accelerator ### Overview This image is a technical block diagram illustrating the system architecture of an Intel/Altera Arria 10 System-on-Chip (SoC) Field-Programmable Gate Array (FPGA). The diagram is divided into two primary domains separated by a horizontal dashed line: the **FPGA** fabric (top) and the **Hard Processor System (HPS)** (bottom). It details the components, memory hierarchy, and data flow pathways for a system designed to accelerate Convolutional Neural Network (CNN) inference. ### Components/Axes The diagram is a component and interconnect map, not a chart with axes. The key elements are: **1. Primary Domains:** * **FPGA:** The programmable logic region, occupying the top half of the diagram. * **HPS (Hard Processor System):** The fixed, hardwired processor region, occupying the bottom half. A label in the bottom-left corner identifies the specific device: **"Arria 10 SoC 20nm FPGA"**. **2. Major Functional Blocks:** * **CNN Inference Accelerator:** A large grey block in the top-center of the FPGA region. * **On-FPGA SRAM Banks:** A large orange block directly below the CNN Accelerator within the FPGA. * **DMA (Direct Memory Access):** A smaller grey block to the left of the CNN Accelerator within the FPGA. * **ARM Cortex-A9 MPCore:** A blue-outlined block in the HPS region. It contains: * **CPU 0** and **CPU 1** * **L1 Caches** (for each CPU) * **ACP** (Accelerator Coherency Port) * **SCU** (Snoop Control Unit) * **L2 Cache:** A block below the ARM Core in the HPS. * **L3 Interconnect:** A large block to the left of the ARM Core/L2 Cache in the HPS. * **SDRAM Controller:** A block below the L2 Cache in the HPS. * **Off-chip DDR4 SDRAM:** A block at the very bottom of the diagram, connected to the SDRAM Controller. **3. Legend (Position: Center-Right):** A small box defines the arrow types: * **Solid Arrow:** Labeled **"Memory Access"**. * **Dashed Arrow:** Labeled **"Configuration Access"**. ### Detailed Analysis **Component Isolation & Spatial Grounding:** * **FPGA Region (Top):** * The **CNN Inference Accelerator** (top-center) has a bidirectional solid arrow (Memory Access) connecting it to the **On-FPGA SRAM Banks** (directly below it). * The **DMA** (left of CNN Accelerator) has: * A bidirectional solid arrow to the **On-FPGA SRAM Banks**. * A bidirectional solid arrow crossing the dashed line to the **HPS** region (specifically connecting to the L3 Interconnect/SDRAM path). * A dashed arrow (Configuration Access) pointing from the **HPS** (specifically from the ARM Core area) to the DMA. * **HPS Region (Bottom):** * The **ARM Cortex-A9 MPCore** (center-right of HPS) has: * A solid arrow pointing down to the **L2 Cache**. * A bidirectional solid arrow connecting to the **L3 Interconnect** (to its left). * A dashed arrow (Configuration Access) pointing up, crossing the dashed line to the **DMA** in the FPGA. * The **L2 Cache** connects via a solid arrow down to the **SDRAM Controller**. * The **L3 Interconnect** has a solid arrow pointing right to the **SDRAM Controller**. * The **SDRAM Controller** has a solid arrow pointing down to the **Off-chip DDR4 SDRAM**. **Data Flow Pathways (Trend Verification):** The primary data movement trends are: 1. **Accelerator Data Path:** Data likely flows from Off-chip SDRAM -> SDRAM Controller -> L3 Interconnect -> DMA -> On-FPGA SRAM Banks -> CNN Inference Accelerator for processing. Results may flow back via the reverse path. 2. **Processor Control Path:** The ARM Core configures the DMA (via Configuration Access) and manages the overall system. It accesses main memory (DDR4) through the L2 Cache and SDRAM Controller. 3. **Coherency Path:** The ACP port on the ARM Core suggests a mechanism to maintain cache coherency between the processor and the FPGA-based accelerator. ### Key Observations 1. **Hierarchical Memory:** The design features a clear memory hierarchy: Off-chip DDR4 (large, slow) -> On-FPGA SRAM (smaller, fast, local to accelerator) -> L2/L1 Caches (processor-local). 2. **Accelerator Isolation:** The CNN Accelerator is physically located in the FPGA fabric but is tightly coupled to dedicated on-chip SRAM for high-bandwidth, low-latency access during inference. 3. **DMA as Bridge:** The DMA controller is the critical bridge between the high-performance FPGA accelerator domain and the general-purpose HPS domain, handling bulk data transfers. 4. **Tight Integration:** The diagram emphasizes the "System-on-Chip" nature, showing the hardwired ARM processors (HPS) and programmable logic (FPGA) on a single die with high-bandwidth interconnects (L3 Interconnect, SDRAM Controller). 5. **Asymmetric Connection:** The connection from the FPGA (DMA) to the HPS is a single, bidirectional memory access path, while the HPS has configuration access *to* the FPGA components. ### Interpretation This diagram illustrates a **heterogeneous computing architecture** optimized for edge AI inference. The design philosophy is to offload the computationally intensive, parallelizable task of CNN inference to a dedicated hardware accelerator in the FPGA fabric, while leaving general-purpose control, pre/post-processing, and system management to the ARM Cortex-A9 processors. * **What it demonstrates:** It shows a practical implementation for achieving high performance and power efficiency in AI applications. The FPGA provides reconfigurable hardware acceleration, the on-FPGA SRAM eliminates the memory bandwidth bottleneck for the accelerator, and the integrated HPS allows for a complete, standalone system without needing a separate host CPU. * **Relationships:** The components form a pipeline. The HPS acts as the master, orchestrating operations and configuring the accelerator via the DMA. The DMA shuttles input data and results between the main system memory (DDR4) and the accelerator's local memory (SRAM). The CNN Accelerator performs the core computation. * **Notable Anomaly/Design Choice:** The use of **DDR4** (instead of DDR3) suggests this is a relatively modern or performance-oriented design, as Arria 10 FPGAs support both. The specific choice of a dual-core **Cortex-A9** (an older ARM core) indicates this may be a cost-optimized or legacy-compatible SoC variant, balancing processing power with the advanced FPGA fabric. The entire system is built on a **20nm process**, which was cutting-edge at its introduction, enabling high logic density and performance.