1809.04028v2

## p-Bits for Probabilistic Spin Logic Kerem Y. Camsari, 1 Brian M. Sutton, 1 and Supriyo Datta 1 School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA (Dated: 13 March 2019) We introduce the concept of a probabilistic or p-bit, intermediate between the standard bits of digital electronics and the emerging q-bits of quantum computing. We show that low barrier magnets or LBM's provide a natural physical representation for p-bits and can be built either from perpendicular magnets (PMA) designed to be close to the in-plane transition or from circular in-plane magnets (IMA). Magnetic tunnel junctions (MTJ) built using LBM's as free layers can be combined with standard NMOS transistors to provide threeterminal building blocks for large scale probabilistic circuits that can be designed to perform useful functions. Interestingly, this three-terminal unit looks just like the 1T/MTJ device used in embedded MRAM technology, with only one difference: the use of an LBM for the MTJ free layer. We hope that the concept of p-bits and p-circuits will help open up new application spaces for this emerging technology. However, a p-bit need not involve an MTJ, any fluctuating resistor could be combined with a transistor to implement it, while completely digital implementations using conventional CMOS technology are also possible. The p-bit also provides a conceptual bridge between two active but disjoint fields of research, namely stochastic machine learning and quantum computing. First, there are the applications that are based on the similarity of a p-bit to the binary stochastic neuron (BSN), a well-known concept in machine learning. Three-terminal p-bits could provide an efficient hardware accelerator for the BSN. Second, there are the applications that are based on the p-bit being like a poor man's q-bit. Initial demonstrations based on full SPICE simulations show that several optimization problems including quantum annealing are amenable to p-bit implementations which can be scaled up at room temperature using existing technology. ## CONTENTS | I. | Introduction | |------|--------------------------------------------| | | A. Between a bit and a q-bit | | | B. Binary stochastic neuron (BSN) | | II. | Hardware Implementation | | | A. Three-terminal p-Bit | | | B. Weighted p-bit | | III. | Applications of p-circuits | | | A. Applications: Machine learning inspired | | | B. Applications: Quantum inspired | | IV. | Conclusions | | | Acknowledgments | | V. | References | ## I. INTRODUCTION ## A. Between a bit and a q-bit Modern digital circuits are based on binary bits that can take on one of two values, 0 and 1, and are stored using well-developed technologies at room temperature. At the other extreme are quantum circuits based on qbits which are delicate superpositions of 0 and 1 requiring the development of novel technologies typically working at cryogenic temperatures. This article is about what we call probabilistic bits or p-bits that are classical entities fluctuating rapidly between 0 and 1. We will argue that we can use existing technology to build what we call pcircuits that should function robustly at room temperature while addressing some of the applications commonly associated with quantum circuits (Fig. 1). How would we represent a p-bit physically? Let us first consider the two extremes, namely the bit and the q-bit. A q-bit is often represented by the spin of an electron, while a bit is often represented by binary voltage levels in digital elements like flip-flops and floating-gate transistors. However, bits can also be represented by magnets 1 which are basically collections of a very large number of spins. In a magnet, internal interactions make the energy a minimum when the spins all point either parallel or anti-parallel to a specific direction, called the easy axis. These two directions represent 0 and 1 and are separated by an energy barrier, E b , that ensures their stability. How large is the barrier? A nanomagnet flips back and forth between 0 and 1 at a rate determined by the energy barrier: τ ∼ τ 0 exp( E b /k B T ) where τ 0 typically has a value between picoseconds and nanoseconds 2 . Assuming a τ 0 of a nanosecond, a barrier of E b ∼ 40 k B T , for example, would retain a 0 (or a 1) for ∼ 10 years, making it suitable for long term memory while a smaller barrier of E b ∼ 14 k B T , would only ensure a short term memory ∼ 1 ms 3 . It has been recognized that this stability problem also represents an opportunity. Unstable low barrier magnets (LBM) could be used to implement useful functions like random number generation (RNG) 4-6 by sensing the randomly fluctuating magnetization to provide a random time varying voltage. With such applications in mind, we would want magnets to have as low a barrier as possible, so that many random numbers are generated in a given amount of time. Indeed a 'zero' barrier magnet with E b ≤ k B T flipping back and forth in less than a nanosecond would be ideal. How can we reduce the energy barrier? Since E b = H K M s Ω / 2, the basic approach is to reduce the total magnetic moment by reducing volume Ω, and/or engineer a small anisotropy field H K 7 . This can be done with perpendicular magnets (PMA) designed to be close to the in-plane transition. A less challenging approach seems to be to use circular in-plane magnets (IMA) 7-9 . We will refer to all these possibilities collectively as LBM's as opposed to say superparamagnets which have more specific connotations in different contexts 3,10-15 . We could use LBM's to represent the probabilistic bits or p-bits that we alluded to. We have argued that if these p-bits can be incorporated into proper transistor-like structures with gain, then the resulting three-terminal p-bits could be interconnected to build pcircuits that perform useful functions 10,12,16 , not unlike the way transistors are interconnected to build useful digital circuits. However, unlike digital circuits these probabilistic p-circuits incorporate features reminiscent of quantum circuits. This connection was nicely articulated by Feynman in a seminal paper 17 , where he described a quantum computer that could provide an efficient simulation of quantum many-body problems. But to set the stage for quantum computers, he first described a probabilistic pcomputer which could efficiently simulate classical manybody problems: . . . 'the other way to simulate a probabilistic nature, which I'll call N . . . is by a computer C which itself is probabilistic, . . . in which the output is not a unique function of the input . . . it simulates nature in this sense: that C goes from some ...initial state . . . to some final state with the same probability that N goes from the corresponding initial state to the corresponding final state . . . If you repeat the same experiment in the computer a large number of times . . . it will give the frequency of a given final state proportional to the number of times, with approximately the same rate . . . as it happens in nature.' There are many practical problems of great interest which involve large networks of probabilistic quantities. These problems should be simulated efficiently by p-computers of the type envisioned by Feynman. Our purpose here is to discuss appropriate hardware building blocks that can be used to build them 16 and possible applications they could be used for. In this context, let us note that although spins provide a nice unifying paradigm for illustrating the transition from bits to p-bits and q-bits, the physical realization of a p-bit need not involve spins or spintronics; non-spintronic implementations can be just as feasible. FIG. 1. Between a bit and a q-bit: The p-bit Digital computers use deterministic strings of 0's and 1's called bits to represent information in a binary code. The emerging field of quantum computing is based on q-bits representing a delicate superposition of 0 and 1 that typically requires cryogenic temperatures. We envision a class of probabilistic computers or p-computers operating robustly at room temperature with existing technology based on p-bits which are classical entities fluctuating rapidly between 0 and 1. Although spins provide a nice unifying paradigm for illustrating the transition from bits to p-bits and q-bits, it should be noted that the physical realization of a p-bit need not involve spins or spintronics; non-spintronic implementations can be just as feasible. <details> <summary>Image 1 Details</summary>  ### Visual Description \n ## Diagram: Computing Paradigms Comparison ### Overview The image is a diagram comparing three computing paradigms: CMOS/Stable Magnets (Digital Computing), Unstable Magnets (p-computing), and Single Spins (Quantum Computing). It visually represents the fundamental differences in how information is stored and processed in each approach. The diagram is divided into three vertical columns, each representing a different paradigm. ### Components/Axes The diagram does not have traditional axes. Instead, it uses a comparative structure with the following key elements: * **Column 1 (Left):** CMOS / Stable Magnets * Information Unit: Bits * State: either 0 or 1 * Operating Temperature: Room temperature * Computing Type: Digital computing * **Column 2 (Center):** Unstable Magnets * Information Unit: p-bits * State: fluctuate between 0 & 1 * Computing Type: p-circuits / p-computing * **Column 3 (Right):** Single Spins * Information Unit: q-bits * State: delicate superposition of 0 & 1 * Computing Type: Quantum computing The text "Room temperature" is highlighted in red. The text "Unstable magnets" and "p-bits" are also highlighted in red. ### Detailed Analysis or Content Details The diagram presents a qualitative comparison rather than quantitative data. Here's a breakdown of each column: * **CMOS / Stable Magnets (Digital Computing):** This represents traditional computing. Information is stored as bits, which can be definitively either 0 or 1. This operates at room temperature. * **Unstable Magnets (p-computing):** This paradigm utilizes p-bits, which are characterized by their fluctuating state between 0 and 1. This suggests a probabilistic or analog nature of information storage. * **Single Spins (Quantum Computing):** This utilizes q-bits, which exist in a "delicate superposition" of 0 and 1. This is a core concept in quantum computing, where a bit can represent both 0 and 1 simultaneously. ### Key Observations The diagram highlights the increasing complexity and nuance in information representation as one moves from digital to p-computing to quantum computing. The use of "fluctuate" and "superposition" indicates a departure from the deterministic nature of classical bits. The red highlighting of "Room temperature", "Unstable magnets", and "p-bits" may indicate a focus on the challenges or unique aspects of p-computing. ### Interpretation The diagram illustrates the evolution of computing paradigms. It suggests that as we move beyond the limitations of classical bits, we encounter systems with more complex and probabilistic states. The diagram implies that p-computing and quantum computing offer potential advantages over traditional digital computing, but also introduce new challenges related to stability and control. The emphasis on "superposition" in quantum computing highlights its potential for parallel processing and solving complex problems that are intractable for classical computers. The diagram is a conceptual overview and does not provide specific performance metrics or technical details. It serves as a high-level comparison of the fundamental principles underlying each computing approach. </details> | Bits either 0 or 1 CMOS/ Stable magnets | p -bits fluctuate between 0 & 1 Unstable magnets | q -bits delicate of 0 & 1 Single spins | |-------------------------------------------|----------------------------------------------------|------------------------------------------| | | | superposition | | Room temperature | Room temperature | | | Digital computing | p - circuits p - computing | Quantum computing | ## B. Binary stochastic neuron (BSN) Interestingly the concept of a p-bit connects naturally to another concept well-known in the field of machine learning, namely that of a binary stochastic neuron (BSN) 18,19 whose response m i to an input I i can be described mathematically by <!-- formula-not-decoded --> where r is a random number uniformly distributed between -1 and +1 20 . Here we are using bipolar variables m i = ± 1 to represent the 0 and 1 states. If we use binary variables m i = 0 , 1 the corresponding equation would look different 21 . When combined with a synaptic function described by <!-- formula-not-decoded --> we have a probabilistic network that can be designed to perform a wide variety of functions through a proper choice of the weights, W ij . A separate bias term h i is often included in Eq. 2 but we will not write it explicitly, assuming that it is included as the weighted input from an extra p-bit that is always +1. Eqs. 1 and 2 are widely used in many modern algorithms but they are commonly implemented in software. Much work has gone into developing suitable hardware accelerators for matrix multiplication of the type described by Eq. 2 (See for example, Ref. 22 ). Threeterminal p-bits would provide a hardware accelerator for Eq. 1. Together they would function like a probabilistic computer. Note that a hardware accelerator for Eq. (1) requires more than just an RNG. We need a tunable RNG whose output m i can be biased through the input terminal I i as shown in Fig. 2. Two distinct designs for a threeterminal p-bit have been described 12,13 both of which use a magnetic tunnel junction (MTJ), a popular 'spintronic' device used in magnetic random access memory (MRAM) 23 . However, MRAM applications use stable MTJ's that can store information for many years, while a p-bit makes use of 'bad' MTJ's with low barriers. The LBM-based implementation of the BSN described here is conceptually very different from a clocked approach using stable magnets where a stochastic output is obtained every time a clock pulse is applied 16,24-30 . All of these approaches work with stable magnets, although LBM's could be used to reduce the switching power that is needed. In this paper we will focus on unclocked, asynchronous operation using LBM-based hardware accelerators for the BSN (Eq. (1)) 10-12 . But can an asynchronous circuit provide the sequential updating of the BSN's described by Eq. (1) that is required for Gibbs sampling 31 and is commonly enforced in software through a for loop ? The answer is 'yes' as shown both in SPICE simulations 10 as well as arduino-based emulations 32 , provided the synaptic function in Eq. (2) has a delay that is less than or comparable to the response time of the BSN, Eq. (1). It should be noted that unclocked operation is a rarity in the digital world and most applications will probably use a clocked, sequential approach with dedicated sequencers that update connected p-bits sequentially. A fully digital implementation of p-circuits using such dedicated sequencers has been realized in Ref. 32 . Synchronous operation can be particularly useful if synaptic delays are large enough to interfere with natural asynchronous operation. Here, we focus on unclocked operation in order to bring out the role of a p-bit in providing a conceptual bridge between two very active fields of research, namely stochastic machine learning and quantum computing . On the one hand p-bits could provide a hardware accelerator for the BSN (Eq. (1)) thereby enabling applications inspired by machine learning ( Section III ). On the other hand, pbits are the classical analogs of q-bits: robust room temperature entities accessible with current technology that could enable at least some of the applications inspired by quantum computing ( Section IV ). But before we discuss applications, let us briefly discuss possible hardware approaches to implementing p-bits ( Section II ). ## II. HARDWARE IMPLEMENTATION ## A. Three-terminal p-Bit RNG's represent an important component of modern electronics and have been implemented using many different approaches, including Johnson-Nyquist noise of FIG. 2. Three terminal p-bit: a. A hardware implementation of the BSN (Eq. (1)) requires a central stochastic element with input and output terminals that provide the ability to read and bias the element. b. The stochastic element can be visualized as going back and forth between two low energy states at a rate that depends exponentially on the barrier E b that separates them: τ = τ 0 exp(∆ /k B T ) c. The bias terminal adjusts the relative energies of the two states thereby controlling the probabilities of finding the element in the two states. <details> <summary>Image 2 Details</summary>  ### Visual Description ## Diagram: Binary Stochastic Neuron & Probability Visualization ### Overview This image presents a conceptual diagram illustrating a binary stochastic neuron (p-bit) and its probabilistic behavior. It consists of a schematic of the neuron, a visualization of energy landscape with noise, and a probability plot showing the relationship between bias and probability. The bottom section shows the energy landscape at different bias values. ### Components/Axes The image is divided into four sections labeled (a), (b), (c), and (d). * **(a): Stochastic Element:** Shows a schematic of the neuron with "BIAS" inputs (blue arrows) and a "READ" output (red box). Inside the neuron is a circle labeled "p". Below this is the text "p-bit: Binary Stochastic Neuron". * **(b): Energy Landscape:** A plot of "Energy" vs. an unspecified axis. It depicts a double-well potential with two states represented by red and blue circles. An arrow labeled "Noise" indicates fluctuations between the states. A delta symbol (Δ) is present on the y-axis. * **(c): Probability vs. Bias Plot:** A plot of "Probability" (y-axis) vs. "Bias" (x-axis). It features three curves: * Red line: labeled "p" * Blue line: labeled "tanh (Bias)" * Green line: labeled "Rolling Average" The background is shaded with purple on the left and light blue on the right. Vertical lines are present throughout the plot. * **(d): Energy Landscapes at Different Biases:** Three energy landscapes are shown, each corresponding to a different bias value. The landscapes are similar to (b), but the position of the red and blue circles changes with increasing bias. Arrows connect these landscapes to the corresponding points on the x-axis of plot (c). ### Detailed Analysis or Content Details * **(a):** The "BIAS" inputs are represented as multiple blue arrows converging on the stochastic element. The output "READ" is a red box. The circle labeled "p" likely represents the probability of the neuron being in the active state. * **(b):** The energy landscape shows two potential wells. The red circle represents a state with lower energy, and the blue circle represents a state with higher energy. The "Noise" arrow indicates that the system can overcome the energy barrier and transition between states. The delta symbol (Δ) is not quantified. * **(c):** * The red line ("p") shows a highly fluctuating probability, with values oscillating between approximately 0 and 1. * The blue line ("tanh(Bias)") is a smooth, sigmoid-shaped curve. It starts near 0 for negative bias values, increases rapidly around bias = 0, and approaches 1 for positive bias values. * The green line ("Rolling Average") is a smoothed version of the red line, showing the overall trend. It also follows a sigmoid shape, similar to the blue line. * The purple shaded region on the left side of the plot corresponds to low probability values, while the light blue shaded region on the right corresponds to high probability values. * **(d):** As the bias increases (from left to right), the energy well corresponding to the blue circle deepens, while the energy well corresponding to the red circle shallows. This indicates that the system is more likely to be in the blue state at higher bias values. ### Key Observations * The stochastic neuron exhibits probabilistic behavior, with the probability of being in the active state (represented by "p") fluctuating significantly. * The "tanh(Bias)" curve provides a deterministic prediction of the probability based on the bias. * The rolling average smooths out the fluctuations and reveals the underlying trend. * The energy landscape visualization helps to understand the physical basis of the probabilistic behavior. ### Interpretation The diagram illustrates how a binary stochastic neuron can be modeled as a system with an energy landscape and noise. The bias controls the shape of the energy landscape, influencing the probability of the neuron being in different states. The noise allows the system to overcome energy barriers and transition between states, resulting in probabilistic behavior. The "tanh(Bias)" curve represents the deterministic component of the probability, while the fluctuations around this curve are due to the noise. The rolling average provides a way to estimate the underlying trend despite the noise. This model is relevant to understanding neural networks and other systems that exhibit stochastic behavior. The diagram suggests that the neuron's behavior is governed by a balance between deterministic bias and random noise. The energy landscape provides a visual metaphor for the decision-making process of the neuron. </details> resistors 33 , phase noise of ring oscillators 34 , process variations of SRAM cells 35 and other physical mechanisms. However, as noted earlier, we need what appears to be a completely new 3-terminal device whose input I i biases its stochastic output m i as shown in Fig. 2c. A recent paper 13 shows that such a 3-terminal tunable RNG can be built simply by combining a 2-terminal fluctuating resistance with a transistor (Fig. 3). This seems very attractive at least in the short run, since the basic structure (Fig. 3a) closely resembles the 1T/MTJ structure commonly used for MRAM applications. The first modification that is required is to replace the stable free layer of the MTJ with an LBM. The second modification is to add an inverter to the drain output that amplifies the fluctuations caused by the MTJ resistance. An MTJ is a device with two magnetic contacts whose electrical resistance R MTJ takes on one of two values R P and R AP depending on whether the magnets are parallel (P) or antiparallel (AP). MTJs are typically used as memory devices, though in recent years applications of MTJs for logic and novel types of computation have been discussed 36-42 . Standard MTJ devices go to great lengths to ensure that the magnets they use are stable and can store information for many years. The resistance of bad MTJ's, on the other hand, constantly fluctuates between R P and R AP 3 . If we put it in series with a transistor which is FIG. 3. Embedded MRAM p-bit: a. An NMOS pulldown transistor in series with a stochastic-MTJ whose resistance fluctuates between RP and R AP as shown in b. c. Using a 14 nm HP-FinFET model 43 the input voltage, V in , versus mid-point, V m , and output V out , voltages is simulated in SPICE. Several fixed resistances are shown to convey how V m would vary with modifications to the parallel and antiparallel resistances. <details> <summary>Image 3 Details</summary>  ### Visual Description \n ## Diagram: LBM-Based Comparator with Conceptual Model and Transfer Characteristics ### Overview The image presents a schematic diagram of a comparator circuit utilizing a Liquid Body Membrane (LBM) and a conceptual model representing its behavior. Below these, a graph illustrates the transfer characteristics of the comparator, showing the relationship between input voltage (Vin), membrane potential (Vm), and output voltage (Vout) under varying conditions. The image is divided into three sections: (a) the circuit schematic, (b) the conceptual model, and (c) the transfer characteristics graph. ### Components/Axes **(a) Circuit Schematic:** * **Components:** Voltage source (VDD/2, -VDD/2), Input voltage (Vin), Liquid Body Membrane (LBM), Inverter, Output voltage (Vout), Ground. * **Labels:** LBM, Vin, Vm, Vout. **(b) Conceptual Model:** * **Components:** Voltage source (VDD/2), Resistors (Rp, RAP), p-bit State, Switch. * **Labels:** VDD/2, Rp, RAP, p-bit State, Vm. **(c) Transfer Characteristics Graph:** * **X-axis:** Vin (Input Voltage), ranging from approximately -0.4 to 0.4. * **Y-axis:** Vm, Vout (Membrane Potential, Output Voltage), ranging from approximately -0.2 to 0.4. * **Legend:** * Vm,100K (Orange dashed line) * Vm,50K (Light Blue dashed line) * Vm,AP (Dark Blue dashed line) * Vm,P (Green dashed line) * Vm,10K (Red dashed line) * Vout,AP (Orange solid line) * Vout (Gray solid line) * Vm (Light Gray solid line) * Vout (Blue solid line) ### Detailed Analysis or Content Details **(a) Circuit Schematic:** The circuit consists of an input voltage (Vin) connected to a Liquid Body Membrane (LBM). The LBM generates a membrane potential (Vm). This potential is then fed into an inverter, producing the output voltage (Vout). The circuit is powered by both positive and negative voltage sources (VDD/2 and -VDD/2). **(b) Conceptual Model:** The conceptual model represents the LBM as a voltage source (VDD/2) in series with a resistor (Rp) and a switch controlled by the p-bit state. The output (Vm) is connected to the switch. Another resistor (RAP) is also present. **(c) Transfer Characteristics Graph:** * **Vm,100K (Orange dashed):** Starts at approximately 0.35 at Vin = -0.4, decreases steadily to approximately 0.05 at Vin = 0, and remains near 0 for Vin > 0. * **Vm,50K (Light Blue dashed):** Similar trend to Vm,100K, but the transition is sharper, starting at approximately 0.3 at Vin = -0.4 and reaching near 0 at Vin = -0.1. * **Vm,AP (Dark Blue dashed):** Starts at approximately 0.3 at Vin = -0.4, decreases rapidly to approximately 0 at Vin = -0.2. * **Vm,P (Green dashed):** Starts at approximately 0.25 at Vin = -0.4, decreases rapidly to approximately 0 at Vin = -0.2. * **Vm,10K (Red dashed):** Starts at approximately 0.35 at Vin = -0.4, decreases rapidly to approximately 0 at Vin = -0.1. * **Vout,AP (Orange solid):** Starts at approximately 0.1 at Vin = -0.4, increases rapidly to approximately 0.35 at Vin = 0, and remains near 0.35 for Vin > 0. * **Vout (Gray solid):** Starts at approximately 0.1 at Vin = -0.4, increases rapidly to approximately 0.35 at Vin = 0, and remains near 0.35 for Vin > 0. * **Vm (Light Gray solid):** Starts at approximately 0.3 at Vin = -0.4, decreases to approximately 0 at Vin = 0. * **Vout (Blue solid):** Shows a sharp transition from approximately 0 to 0.35 around Vin = 0. ### Key Observations * The transfer characteristics of Vm vary significantly with the parameter indicated by the suffix (100K, 50K, AP, P, 10K). Lower values lead to sharper transitions. * Vout exhibits a hysteresis effect, with a clear switching threshold around Vin = 0. * The Vout,AP curve closely follows the Vout curve, suggesting that the "AP" parameter has a minimal impact on the output. * The Vm curves all exhibit a decreasing trend as Vin increases, indicating an inverse relationship. ### Interpretation The diagram illustrates the operation of a comparator circuit utilizing a Liquid Body Membrane (LBM). The LBM acts as a voltage-dependent resistor, influencing the membrane potential (Vm). The conceptual model simplifies this behavior by representing the LBM as a voltage source and resistor network. The transfer characteristics graph demonstrates the comparator's ability to switch between two voltage levels based on the input voltage (Vin). The different curves for Vm represent variations in the LBM's properties, such as resistance or ion concentration, which affect the comparator's sensitivity and switching speed. The hysteresis observed in Vout is a typical characteristic of comparators and is crucial for preventing oscillations near the switching threshold. The curves suggest that the comparator is designed to operate as a threshold detector, switching its output state when Vin crosses a certain value. The parameters 100K, 50K, AP, P, and 10K likely represent different configurations or operating conditions of the LBM, influencing its performance. The graph provides valuable insights into the comparator's behavior and can be used to optimize its design for specific applications. </details> a voltage controlled resistance R T ( V in ) then the voltage V m (Fig. 3) can be written as <!-- formula-not-decoded --> The magnitude of this fluctuating voltage V m is largest when the transistor resistance R T ∼ R P or R AP but gets suppressed if R T R P or if R T R AP . The input voltage controls R T thereby tuning the stochastic output V m as shown in Fig. 3c. It was shown that an additional inverter provides an output that is approximately described by an expression that looks just like the BSN (Eq. 1) <!-- formula-not-decoded --> but with dimensionless variables like m i and I i replaced by scaled circuit voltages V out and V in . The scheme in Fig. 3 provides tunability through the series transistor and does not involve the physics of the fluctuating resistor. Ideally, the magnet is unaffected by the change in the transistor resistance though the drain current, in principle, could pin the magnet. In our simulations that are based on Ref. 13 , we take the pinning current into account through a spin-polarized current ( I s ) proportional to an effective fixed layer polarization and the drain current ( I D ), I s = ( P ) I D ˆ x , where ˆ x is the fixed layer direction. This spin-current enters the sLLG equation that calculates an instantaneous magnetization which in turn controls the MTJ resistance. We note that any significant pinning around zero input voltage V in,i has to be minimized through proper design, especially for low barrier perpendicular magnets which are relatively easy to pin. Unintentional pinning 44 should in general not be an issue for circular in-plane LBM's due to the strong demagnetizing field. The pinning behavior for the average (steady-state) magnetization can be qualitatively understood by numerical simulations of the sLLG equation. In the case of low-barrier perpendicular magnets the spin-torque pinning needs to overcome the thermal noise and therefore the pinning current is of order I PMA ≈ 2( q/ ) αkT where α is the damping coefficient of the magnet. In the case of circular in-plane magnets, the pinning current is of order I IMA ≈ 2( q/ ) αH D M s Vol . , which is much larger than I PMA since for for typical parameters ( H D M s Vol . kT ). Since the state of the magnet is not affected, if the input voltage V in,i in Eq. 3 is changed at t=0, the statistics of the output voltage V out,i will respond within tens of picoseconds (typical transistor switching speeds) 45 irrespective of the fluctuation rates of the magnet. However, the magnet fluctuations will determine the correlation time of the random number r in Eq. 3. Alternatively one can envision structures where the input controls the statistics of the fluctuating resistor itself, through phenomena such as the spin-Hall effect 12 or the magneto-electric effect 46 based on a voltage control of magnetism (see for example 47,48 ). In that case, both the speed of response and the correlation time of the random number r will be determined by the specific phenomenon involved. Non-spintronic implementations: Note that the structure in Fig. 3 could use any fluctuating resistor including CMOS-based units in place of the MTJ showing that the physical realization of a p-bit need not involve spins 49 . For example, a linear feedback shift register (LFSR) is often used to generate a pseudo-randomly fluctuating bit stream 50 . We can apply this fluctuating voltage to the gate of a transistor to obtain a fluctuating resistor which can replace the MTJ in Fig. 3a. We note that the main appeal of the structure in Fig. 3 lies in its simplicity, since a 1T/1MTJ design coupled with two more transistors provide the tunable randomness in a compact transistorlike building block. Using completely digital p-circuit implementations 32 could offer short term scalability and reliability but they would consume a much larger area and power per p-bit. ## B. Weighted p-bit The structure in Fig. 3 gives us a 'neuron' that implements Eq. 1 in hardware. Such neurons have to be used in conjunction with a 'synapse' that implements FIG. 4. Example of a weighted p-bit integrating relevant parts of the synapse onto the neurons: Leveraging floating-gate devices along the lines proposed in neuMOS 51 devices, a collection of synapse inputs (from 1 to n) can be summed to produce the bias voltage, V IN ,i for a voltage driven p-bit 52 . <details> <summary>Image 4 Details</summary>  ### Visual Description \n ## Diagram: Neural Network Input Stage with LBM ### Overview The image depicts a schematic diagram of an input stage for a neural network, incorporating a Local Binary Memory (LBM). The diagram shows a series of input voltages (Vbias,i, Vout,j, Vout,j+n) connected to a transistor stack, which then feeds into an LBM element. The output of the LBM is then processed by an inverter to produce the final output voltage (Vout,i). Two equations are provided below the diagram. ### Components/Axes The diagram consists of the following components: * **Input Voltages:** Vbias,i, Vout,j, Vout,j+n. * **Transistor Stack:** A series of transistors connected between +VDD/2 and -VDD/2. * **LBM (Local Binary Memory):** Represented as a cylindrical capacitor with blue and yellow bands. * **Inverter:** A standard CMOS inverter. * **Voltage Sources:** +VDD/2 and -VDD/2. * **Intermediate Voltage:** Vm. * **Equations:** Eq. (1) and Eq. (2). ### Content Details The diagram can be divided into three main sections: the input stage, the LBM, and the output stage. **Input Stage:** * Multiple input voltages are present: Vbias,i, Vout,j, and Vout,j+n. The "..." indicates that there are potentially more Vout inputs. * These inputs are connected to the gates of transistors in the stack. * The transistor stack is connected to +VDD/2 at the top and -VDD/2 at the bottom. **LBM:** * The output of the transistor stack is connected to one terminal of the LBM. * The other terminal of the LBM is connected to a voltage source Vm. * The LBM is connected to an inverter. **Output Stage:** * The output of the inverter is labeled Vout,i. **Equations:** * **Eq. (1):** m_i = sgn[tanh I_i – r] * **Eq. (2):** I_i = Σ w_ij m_j Where: * m_i and m_j are likely binary memory states. * I_i is a current. * w_ij are weights. * r is a threshold. * sgn is the sign function. ### Key Observations * The diagram illustrates a neural network architecture that utilizes a local binary memory element. * The LBM appears to be a key component in the network's functionality. * The equations suggest a weighted sum of binary memory states is used to calculate a current, which is then used to determine the memory state. * The dashed vertical line separates the input stage from the LBM and output stage. ### Interpretation The diagram represents a simplified model of a neural network input stage. The transistor stack acts as a current source or sink, controlled by the input voltages. The LBM stores binary information, and the equations suggest that the network learns by adjusting the weights (w_ij) to modify the current flow and, consequently, the memory states. The inverter provides a logic function to produce the final output. The use of an LBM suggests a focus on low-power or analog computation. The equations provide a mathematical description of the LBM's operation, indicating a threshold-based activation function (tanh and sgn). The overall architecture suggests a system capable of pattern recognition or classification based on the weighted sum of inputs and the stored binary information. The diagram is a conceptual representation and does not specify the exact implementation details of the transistors or the LBM. </details> Eq. 2. Alternatively we could design a 'weighted p-bit' that integrates each element of Eq. 1 with the relevant part of Eq. 2. For example, we could use floating gate devices along the lines proposed in neuMOS 51 devices as shown in Fig. 4. From charge conservation we can write <!-- formula-not-decoded --> where C 0 is the input capacitance of the transistor. This can be rewritten as <!-- formula-not-decoded --> By scaling V in and V out (see Eq. 3) to play the roles of the dimensionless quantities I i and m i respectively, we can recast Eq. 4 in a form similar to Eq. 2: <!-- formula-not-decoded --> The weights W ij can be adjusted by controlling the specific capacitors C ij that are connected. The range of allowed weights and connections is then limited by the routing topology and neuMOS device size. Note that the control of weights through C ij works best if C 0 ∑ j C ij so that W i,j ≈ C i,j /C 0 , however it is possible to design a weighted p-bit design without this assumption ( C 0 ∑ C ij ) as discussed in detail in Ref. 52 . Similar control can also be achieved through a network of resistors. The weights are given by the same expression, but with capacitances C ij replaced by conductances G ij 22 . However, the input conductance G 0 of FET's is typically very low, so that an external conductance has to be added to make G 0 ∑ j G ij . ## III. APPLICATIONS OF P-CIRCUITS As noted earlier, real applications involve p-bits interconnected by a synapse that can be implemented off-chip either in software or with a hardware matrix multiplier, but then it is necessary to transfer data back and forth between Eq. 1 and Eq. 2. Therefore, a low-level compact hardware implementation of a p-bit along with a local synapse as envisioned in Fig. 4 could be a hardware accelerator for many types of applications, some of which will be discussed in this section. In the capacitvely weighted p-bit design of Fig. 4, the weights and connectivity of the of the p-bit could be dynamically adjusted based on the encoding of a given problem by leveraging a network of programmable switches 53 as would be encountered in FPGAs. Such a p-bit with local interconnections would look like a compact nanodevice implementation of highly scaled digital spiking neurons of neuromorphic chips such as TrueNorth 54 . Alternatively, the interconnection function could be performed off-chip using standard CMOS devices such as FPGAs or GPUs while p-bits are implemented in a standalone chip by modifying embedded MRAM technology. Note however, the off-chip implementation of the interconnection matrix would impose a timing constraint for an asynchronous mode of operation, which requires the weighted summation operation (Eq. 2) to operate much faster than the p-bit operation (Eq. 1) for proper convergence 10,55 . A full on-chip implementation of a reconfigurable p-bit could function as a low-power, efficient hardware accelerator for applications in Machine Learning and Quantum Computing, but in the near term a heterogenous multi-chip synapse / p-bit combination could also prove to be useful. Now that we have discussed some possible approaches to implementing Eqs. 1 and 2 in hardware, let us present a few illustrative p-bit networks that can implement useful functions and can be built using existing technology. Unless otherwise stated, these results are obtained from full SPICE simulations 56 that solve the stochastic Landau-Lifshitz-Gilbert equation coupled with the PTMbased transistor models in SPICE 43 to model the embedded MTJ based 3-terminal p-bit described in Fig. 3. ## A. Applications: Machine learning inspired Bayesian inference: A natural application of stochastic circuits is in the simulation of networks whose nodes are stochastic in nature (See for example 16,57-59 ). An archetypal example is a genetic network, a small version of which is shown in Fig. 5. A well-known concept is that of genetic correlation or relatedness between different members of a family tree. For example, assuming that each of the children C 1 and C 2 get half their genes from their parents F 1 and M 1 we can write their correlation as: <!-- formula-not-decoded --> assuming F 1 and M 1 are uncorrelated. Hence the wellknown result that siblings have 50% relatedness. Similarly one can work out the relatedness of more distant relationships like that of an aunt M 1 and her nephew C 3 which turns out to be 25%. The point is that we could construct a p-circuit with each of the nodes represented by a hardware p-bit interconnected to reflect the genetic influences. The correlation between two nodes, say C 1 and C 2 , is given by <!-- formula-not-decoded --> If C 1 (t) and C 2 (t) are binary variables with allowed values of 1 and 0, then they can be multiplied in hardware with an AND gate. If the allowed values are bipolar, -1 and +1, then the multiplication can be implemented with an XNOR gate. In either case the average over time can be performed with a long time constant RCcircuit. A few typical results from SPICE simulations are shown in Fig. 5. The numerical results in Fig. 5 are in good agreement with Bayes theorem even though the circuit operates asynchronously without any sequencers. This is interesting since software simulations of Eqs. 1 and 2 with directed weights usually require the nodes to be updated from parent to child. Whether this behavior generalizes to larger directed networks is left for future work. We use this genetic circuit as a simple illustration of the concept of nodal correlations which appear in many other contexts in everyday life. Medical diagnosis 60 , for example, involve symptoms such as, say high temperature, which can have multiple origins or parents and one can construct Bayesian networks to determine different causal relationships of interest. Accelerating learning algorithms: Networks of pbits could be useful in implementing inference networks, where the network weights are trained offline by a learning algorithm in software and the hardware is used to repeatedly perform inference tasks efficiently 61,62 . Another common example where correlations play an important role is in the learning algorithms used to train modern neural networks like the restricted Boltzmann machine (Fig. 6) 63 having a visible layer and a hidden layer, with connecting weights W ij linking nodes of one layer to those in the other, but not within a layer. A widely used algorithm based on 'contrastive FIG. 5. Genetic circuit: C1 and C2 are siblings with parents F1, M1, while C3 and C4 are siblings with parents F2, M2. Two of the parents M1 and F2 are siblings with parents GF1, GM1. Genetic correlations between different members can be evaluated from the correlations of the nodal voltages in a p-circuit. An XNOR gate finds their product while a long time constant RC circuit provides the time average. <details> <summary>Image 5 Details</summary>  ### Visual Description ## Diagram & Chart: Correlation Analysis of a Circuit ### Overview The image presents a combination of a circuit diagram and a correlation chart. The circuit diagram depicts a network of components including XOR gates, resistors, and capacitors. The chart displays the correlation between different signal pairs within the circuit as a function of time. The chart is labeled "Correlation". ### Components/Axes **Circuit Diagram Components:** * **Inputs:** C1, C2, C3, C4 * **Intermediate Nodes:** M1, M2, F1, F2 * **Outputs:** GF1, GM1 * **Gate:** XNOR * **Passive Components:** Resistor (R), Capacitor (C) * **Equation:** ∫₀ᵀ (d/dt C1(t)C2(t)) dt / T **Correlation Chart Components:** * **X-axis:** Time (ns), ranging from 0 to 500. * **Y-axis:** Correlation value, ranging from approximately 0 to 0.55. * **Data Series:** * (M1 x C2) - Green line * (C1 x C2) - Dark Green line * (C3 x M1) - Purple line * (C2 x F2) - Orange line * (F1 x M2) - Blue line * **Horizontal dashed lines:** at approximately 0.25 and 0.5. ### Detailed Analysis or Content Details **Circuit Diagram:** The circuit diagram shows a network where inputs C1, C2, C3, and C4 feed into intermediate nodes M1, M2, F1, and F2. These nodes are connected to outputs GF1 and GM1 through what appears to be an XNOR gate. A resistor (R) and capacitor (C) are shown connected to ground. The equation below the circuit diagram represents an integral calculation involving the time derivatives of signals C1 and C2. **Correlation Chart:** * **(M1 x C2):** The green line starts at approximately 0 at time 0 ns, rises rapidly to around 0.45 by 100 ns, and then plateaus around 0.5, with some fluctuations. * **(C1 x C2):** The dark green line starts at approximately 0 at time 0 ns, rises rapidly to around 0.5 by 100 ns, and then plateaus around 0.5, with some fluctuations. * **(C3 x M1):** The purple line starts at approximately 0 at time 0 ns, rises to around 0.3 by 100 ns, and then plateaus around 0.3, with some fluctuations. * **(C2 x F2):** The orange line starts at approximately 0 at time 0 ns, rises to around 0.25 by 100 ns, and then plateaus around 0.25, with some fluctuations. * **(F1 x M2):** The blue line starts at approximately 0 at time 0 ns, rises to around 0.1 by 100 ns, and then remains relatively flat around 0.1, with some fluctuations. ### Key Observations * The correlation between (C1 x C2) and (M1 x C2) is the highest, reaching a plateau around 0.5. * The correlation between (F1 x M2) is the lowest, remaining near 0.1 throughout the observed time period. * All correlation curves show an initial rise within the first 100 ns, suggesting an initial correlation development. * The dashed lines at 0.25 and 0.5 provide reference points for evaluating the correlation strength. ### Interpretation The image demonstrates the correlation between different signal pairs within a circuit. The circuit appears to be designed to amplify or enhance the correlation between certain signals, as evidenced by the high correlation values between (C1 x C2) and (M1 x C2). The lower correlation between (F1 x M2) suggests a weaker relationship or a different processing path within the circuit. The integral equation likely represents a method for calculating the correlation between signals C1 and C2 over time. The XNOR gate suggests a comparison or difference operation is being performed. The correlation chart provides insight into how signals propagate and interact within the circuit, potentially revealing bottlenecks or areas of strong signal coupling. The time scale (ns) indicates that the circuit operates at a relatively high speed. The horizontal dashed lines may represent thresholds for signal detection or decision-making within the circuit. </details> divergence' 64 adjusts each weight W ij according to <!-- formula-not-decoded --> which requires the repeated evaluation of the correlations 〈 v i h j 〉 . Computing such correlations exactly becomes intractable due to their exponential complexity in the number of neurons, therefore contrastive divergence is often limited by a fixed number of steps (CDn) to limit the number of repeated evaluation of these correlations. This process could be accelerated through an efficient physical representation of the neuron and the synapse 65,66 . ## B. Applications: Quantum inspired The functionality of neural networks is determined by the weight matrix W ij which determines the connectivity among the neurons. They can be classified broadly by the relation between W ij and W ji . In traditional feedforward networks, information flow is directed with neuron 'i' influencing neuron 'j' through a non-zero weight W ij but with no feedback from neuron 'j' , such that W ji = 0. At the other end of the spectrum, is a network with all connections being reciprocal W ij = W ji . In between these two extremes are the class of networks for which the weights between two nodes are asymmetric, but non-zero. The class of networks with symmetric connections is particularly interesting since they have a close parallel with classical statistical physics where the natural connections between interacting particles is symmetric and the equilibrium probabilities are given by the celebrated Boltzmann law expressing the probability of a particular configuration α in terms of an energy E α associated with FIG. 6. Restricted Boltzmann Machine (RBM): RBMs are a special class of stochastic neural networks that restrict connections within a hidden and a visible layer. Standard learning algorithms require repeated evaluations of correlations of the form 〈 v i h j 〉 . <details> <summary>Image 6 Details</summary>  ### Visual Description \n ## Diagram: Data Flow Representation ### Overview The image depicts a diagram illustrating a data flow or mapping between two sets of elements. A top rectangular block labeled with variables `v1` to `vn` is connected to a bottom rectangular block labeled with variables `h1` to `hm` via a series of directed arrows. The diagram appears to represent a function or transformation that maps elements from the top set to elements in the bottom set. ### Components/Axes The diagram consists of two rectangular blocks and a set of directed arrows. * **Top Block:** Filled with a light blue color. Labeled with `v1` on the left and `vn` on the right, with ellipsis (`....`) indicating intermediate elements. * **Bottom Block:** Filled with a light green color. Labeled with `h1` on the left and `hm` on the right, with ellipsis (`....`) indicating intermediate elements. * **Arrows:** Black, directed arrows connecting elements from the top block to the bottom block. The arrows point downwards, indicating a mapping or transformation. ### Detailed Analysis or Content Details The diagram shows a mapping from a set of `n` variables (v1 to vn) to a set of `m` variables (h1 to hm). The arrows indicate that each variable in the top set can potentially map to one or more variables in the bottom set. The exact nature of the mapping is not specified, but the arrows suggest a functional relationship. There are four arrows shown. * The first arrow originates approximately from the center of the left side of the top block and points to the left side of the bottom block. * The second arrow originates approximately from the center of the top block and points to the center of the bottom block. * The third arrow originates approximately from the center of the top block and points to the right side of the bottom block. * The fourth arrow originates approximately from the right side of the top block and points to the right side of the bottom block. ### Key Observations The diagram highlights a relationship between two sets of variables. The use of ellipsis suggests that the number of variables in each set is not limited to the explicitly labeled ones. The arrows indicate a directed mapping, but the diagram does not specify whether the mapping is one-to-one, one-to-many, or many-to-one. ### Interpretation This diagram likely represents a function or transformation that maps input variables (v1 to vn) to output variables (h1 to hm). It could be a simplified representation of a neural network layer, a feature extraction process, or any other mapping operation. The diagram emphasizes the flow of information from the input set to the output set. The lack of specific details about the mapping function suggests that the diagram is intended to be a general illustration of a data flow concept rather than a specific implementation. The diagram does not provide any quantitative data or specific values, but it conveys the essential idea of a mapping between two sets of variables. </details> that configuration. <!-- formula-not-decoded --> <!-- formula-not-decoded --> where T denotes transpose and the constant Z is chosen to ensure that all P ′ α s add up to one. This energy principle is only available for reciprocal networks 67 , and can be very useful in determining the appropriate weights W ij for a particular problem. This class of networks connects naturally to the world of quantum computing which is governed by Hermitian Hamiltonians, and is also the subject of the emerging field of Ising computing 10,16,68-72 . Invertible Boolean logic: Suppose, for example, we wish to design a Boolean gate which will provide three outputs reflecting the AND, OR and XNOR functions of the two inputs A and B. The truth table is shown in Fig. 7. Note that although we are using the binary notation 1 and 0, they actually stand for p-bit values of +1 and -1 respectively. Since there are five p-bits, two representing the inputs and three representing the outputs, the system has 2 5 = 32 possible states, which can be indexed by their corresponding decimal values. Each of these configurations has an associated energy, E n , n = 0 , 1 , . . . , 31 . What we need is a weight matrix W ij such that the desired configurations 4, 9, 17 and 31 (in decimal notation) specified by the truth table have a low energy E α (Eq. (8)) compared to the rest, so that they are occupied with higher probability. This can be done either by using the principles of linear algebra 12 or by using machine learning algorithms 73 to obtain the weight matrix shown in Fig. 7. Note that an additional p-bit labeled 'h' has been introduced which is clamped to a value of +1 by applying a large bias. On the right of Fig. 7, a histogram is showing the frequency of all the possible (32) configurations obtained from a simulation of Eq. (1) and Eq. (2) using this weight matrix. Similar results are obtained from a SPICE simulation of a p-circuit of weighted p-bits. Note the peaks at the desired truth table values, with smaller peaks at some of the undesired values. The peaks closely follow FIG. 7. Invertible Boolean logic: A multi-function Boolean gate with 6 p-bits is shown. Inputs A and B produce the output for a 2-input XNOR, AND and OR gate, respectively. The handle bit, 'h' is used to remove the complementary low-energy states that do not belong to the truth table shown. In the unclamped mode, the system shows the states corresponding to the the lines of the truth table with high probability. A and B can be clamped to produce the correct output for the XNOR, AND and OR in the direct mode. In the inverse mode, any one of the outputs (XNOR is shown as an example) can be clamped to a given value, and the inputs fluctuate among possible input combinations corresponding to this output. <details> <summary>Image 7 Details</summary>  ### Visual Description \n ## Charts/Diagrams: Boolean Function Analysis & State Probabilities ### Overview The image presents an analysis of Boolean functions (XNOR, AND, OR) using a truth table, a weight matrix, and probability distributions of states. The distributions appear to represent the probabilities of different states arising from the functions. There are four charts in total: a truth table, a weight matrix, and three histograms representing probability distributions. ### Components/Axes * **Truth Table:** Columns labeled 'A', 'B', 'XNOR', 'AND', 'OR', 'Decimal'. Rows represent the input combinations (0,0), (0,1), (1,0), (1,1). * **Weight Matrix:** Rows and columns labeled 'h', 'A', 'B', 'XNOR', 'AND', 'OR'. Values within the matrix are +1 or -1. * **Histogram 1 (Top-Right):** X-axis labeled 'states', Y-axis labeled 'Probability'. The x-axis ranges from approximately 0 to 32. The histogram has peaks labeled '4', '9', '17', and '31'. * **Histogram 2 (Bottom-Left):** X-axis labeled 'states', Y-axis labeled 'Probability'. The x-axis ranges from approximately 0 to 32. Peaks are labeled '9' and '17'. Text annotation: "XNOR → 0". * **Histogram 3 (Bottom-Right):** X-axis labeled 'states', Y-axis labeled 'Probability'. The x-axis ranges from approximately 0 to 32. Peak is labeled '17'. Text annotation: "A → 1", "B → 0". ### Detailed Analysis or Content Details **Truth Table:** | A | B | XNOR | AND | OR | Decimal | |---|---|---|---|---|---| | 0 | 0 | 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 0 | 1 | 2 | | 1 | 0 | 0 | 0 | 1 | 2 | | 1 | 1 | 1 | 1 | 1 | 3 | **Weight Matrix:** | h | A | B | XNOR | AND | OR | |---|---|---|---|---|---| | h | 0 | 0 | 0 | +1 | -1 | +1 | | A | 0 | 0 | +1 | 0 | -1 | -1 | | B | 0 | +1 | 0 | 0 | -1 | -1 | | XNOR | +1 | 0 | 0 | -1 | 0 | -1 | | AND | +1 | 0 | -1 | 0 | 0 | 0 | | OR | -1 | +1 | -1 | 0 | 0 | 0 | **Histogram 1 (Top-Right):** The histogram shows a distribution of probabilities across states. The highest probability is approximately 0.11 at state 9 and 17. There are smaller peaks at states 4 and 31, with probabilities around 0.09. The probability generally decreases between peaks. * State 4: ~0.09 * State 9: ~0.11 * State 17: ~0.11 * State 31: ~0.09 **Histogram 2 (Bottom-Left):** This histogram shows a bimodal distribution with peaks at states 9 and 17. The probability at state 9 is significantly higher, approximately 0.24. The probability at state 17 is approximately 0.16. * State 9: ~0.24 * State 17: ~0.16 **Histogram 3 (Bottom-Right):** This histogram shows a unimodal distribution with a strong peak at state 17. The probability at state 17 is approximately 0.35. * State 17: ~0.35 ### Key Observations * The truth table defines the behavior of the XNOR, AND, and OR functions for all possible input combinations. * The weight matrix appears to represent the weights associated with each variable and function in a neural network or similar model. * The histograms show the probability distributions of states resulting from the Boolean functions. * Histogram 2 (XNOR → 0) has peaks at states 9 and 17, suggesting these states are more likely when the XNOR function outputs 0. * Histogram 3 (A → 1, B → 0) has a strong peak at state 17, indicating this state is highly probable when A is 1 and B is 0. * The first histogram shows a more even distribution of probabilities across multiple states. ### Interpretation The image demonstrates a connection between Boolean logic, weighted representations, and probabilistic state distributions. The truth table and weight matrix define the underlying logic, while the histograms visualize the resulting probabilities of different states. The annotations on the bottom histograms suggest a specific scenario where the XNOR function is forced to output 0, and another where A is 1 and B is 0. The differing distributions in each histogram indicate that the output probabilities are highly dependent on the input conditions and the underlying Boolean function. The weight matrix could be used to implement these functions in a neural network, and the histograms represent the network's output distribution. The data suggests that the XNOR function, when constrained to output 0, leads to a distribution favoring states 9 and 17, while the condition A=1, B=0 strongly favors state 17. The first histogram shows a more uniform distribution, indicating a less constrained or more complex scenario. </details> the Boltzmann law, such that <!-- formula-not-decoded --> Undesired peaks can be suppressed if we make the Wmatrix larger, say by an overall multiplicative factor of 2. If all energies are increased by a factor of 2, the ratio of probabilities would be squared: a ratio of 10 would become a ratio of 100. It is also possible to operate the gate in a traditional feed-forward manner where inputs are specified and an output is obtained. This mode is shown in the middle panel on the right where the inputs A and B are clamped to 1 and 0 respectively. Only one of the four truth table peaks can be seen, namely the line corresponding to A=1, B=0, which is labeled 17. What is more interesting is that the gates can be run in inverse mode as shown in the lower right panel. The XNOR output is clamped to 0 corresponding to specific lines of the truth table corresponding to 9 and 17. The inputs now fluctuate between the two possibilities, indicating that we can use these gates to provide us with all possible inputs consistent with a specified output, a mode of operation not possible with standard Boolean gates. FIG. 8. Combinatorial Optimization: A 5-city Traveling Salesman Problem (TSP) implemented using a network of 16 p-bits (fixing city 0), each having two indices, the first denoting the order in which a city is visited and the second denoting the city. The interaction parameter I 0 scales all weights and acts as an inverse temperature and is slowly increased via a simple annealing schedule I 0 ( t + t eq ) = ( 1 / 0 . 99 ) I 0 ( t ) to guide the system into the lowest energy state, providing the shortest traveling distance (Map imagery data: Google, TerraMetrics). <details> <summary>Image 8 Details</summary>  ### Visual Description \n ## Scatter Plot & Heatmaps: City Visit Energy Analysis ### Overview The image presents a scatter plot alongside a map illustrating city visits, and three heatmaps showing relationships between city visits. The scatter plot displays normalized energy against a variable labeled "I₀" on a logarithmic scale. The map shows a route connecting several cities, numbered 0 through 4. The heatmaps visualize the correlation between city number and order of city visits. ### Components/Axes * **Scatter Plot:** * X-axis: "I₀" (Logarithmic scale, ranging approximately from 10⁻¹ to 10²). * Y-axis: "Normalized energy" (ranging from 0 to approximately 0.9). * **Map:** * Cities are labeled 0, 1, 2, 3, and 4. * Red lines connect the cities in a specific order. * **Heatmaps:** * X-axis: "Order of city visits" (1, 2, 3, 4). * Y-axis: "City Number" (1, 2, 3, 4). * Color scale: Ranges from -1 (dark blue) to 1 (yellow). * **Legend (Heatmaps):** Located on the right side of the heatmaps, indicating the color scale corresponds to values from -1 to 1. ### Detailed Analysis or Content Details **Scatter Plot:** The scatter plot shows a strong negative correlation. The data points are densely clustered on the left side (low I₀ values, high normalized energy) and become increasingly sparse as I₀ increases. The trend is a downward slope, indicating that as I₀ increases, normalized energy decreases. * At I₀ ≈ 10⁻¹, normalized energy is approximately 0.7-0.8. * At I₀ ≈ 1, normalized energy is approximately 0.2-0.3. * At I₀ ≈ 10², normalized energy is approximately 0.01-0.05. **Map:** The map shows a route starting at city 0, then to 1, 3, 2, and finally back to 0. The cities appear to be located in the United States. * City 0: Appears to be in the Northeast US. * City 1: Appears to be in the Midwest US. * City 2: Appears to be in the Southwest US. * City 3: Appears to be in the South-Central US. * City 4: Appears to be in the Pacific Northwest US. **Heatmaps:** The heatmaps show the correlation between city number and order of city visits. Each heatmap represents a different perspective or parameter set. * **Heatmap 1 (Left):** Shows a mix of positive and negative correlations. City 1 and 2 have a moderate positive correlation with order 1 and 2. City 3 and 4 have a moderate negative correlation with order 3 and 4. * **Heatmap 2 (Center):** Shows a more pronounced pattern. City 1 has a positive correlation with order 1. City 2 has a positive correlation with order 2. City 3 has a positive correlation with order 3. City 4 has a positive correlation with order 4. * **Heatmap 3 (Right):** Shows a very strong positive correlation. City 1 has a strong positive correlation with order 1. City 2 has a strong positive correlation with order 2. City 3 has a strong positive correlation with order 3. City 4 has a strong positive correlation with order 4. ### Key Observations * The scatter plot demonstrates a clear inverse relationship between I₀ and normalized energy. * The map illustrates a specific sequence of city visits. * The heatmaps reveal correlations between city number and the order in which they are visited, with the correlation strength increasing from left to right. * The heatmaps suggest a strong preference for visiting cities in a specific order. ### Interpretation The data suggests an analysis of energy expenditure or some other quantifiable metric related to a sequence of city visits. The scatter plot likely represents the energy required to travel between cities as a function of some parameter I₀, which could be distance, time, or a combination of factors. The negative correlation indicates that as I₀ increases, the energy required decreases, potentially due to optimization or efficiency gains. The map provides the context for the data, showing the specific route taken. The heatmaps then quantify the relationships between the cities and the order in which they are visited. The increasing correlation strength across the heatmaps suggests that the model or algorithm used to analyze the data is converging on a preferred sequence of city visits. The strong positive correlation in the rightmost heatmap indicates a high degree of predictability or preference for visiting cities in a specific order. This could be due to factors such as travel costs, time constraints, or the inherent structure of the network of cities. The data could be used to optimize travel routes, predict future city visits, or understand the underlying patterns of human movement. </details> This invertible mode is particularly interesting because there are many cases where the direct problem is relatively easy compared to the inverse problem. For example, we can find a suitable weight matrix to implement an adder that provides the sum S of numbers A, B and C. But the same network also solves the inverse problem where a sum S is provided and it finds combinations of k numbers that add up to S 32,52 . This inverse k-sum or subset sum problem is known to be NP-complete 74 and is clearly much more difficult than direct addition. Similarly we can design a weight matrix such that the network multiplies any two numbers. In inverse mode the same network can factorize a given number, which is a hard problem 75 . This ability to factorize has been shown with relatively small numbers 12,32 . How well p-circuits will scale to larger factorization problems remains to be explored. It is worth mentioning that this method of solving integer factorization and the subset sum problem is similar to the deterministic 'memcomputing' framework where a 'self-organizing logic circuit' is set up to solve the direct problem and operated in reverse to solve the inverse problem (See for example, Ref. 76,77 ). Optimization by classical annealing: It has been shown that many optimization problems can be mapped onto a network of classical spins with an appropriate weight matrix, such that the optimal solution corresponds to the configuration with the lowest energy 78 . Indeed, even the problem of integer factorization discussed above in terms of inverse multiplication can alternatively be addressed in this framework by casting it as an optimization problem 79-81 . A well-known example of an optimization problem is the classic N-city traveling salesman problem (TSP). It involves finding the shortest route by which a salesman can visit all cities once starting from a particular one. This problem has been mapped to a network of ( N -1) 2 spins where each spin has two indices, the first denoting the order in which a city is visited and the second denoting the city. Fig. 8 shows a 5-city TSP mapped to a 16 p-bit network and translated into a p-circuit that is simulated using SPICE. The overall W-matrix is slowly increased and with increasing interaction the network gradually settles from a random state into a low energy state. This process is often called simulated annealing 82 based on the similarity with the freezing of a liquid into a solid with a lowering of temperature in the physical world, which reduces the random thermal energy relative to a fixed interaction. Note that at high values of interaction the p-bits settle to the correct solution with four p-bits highlighted corresponding to (1,1), (2,3), (3,2) and (4,4), showing that the cities should be visited in the order 1-3-2-4. Unfortunately things may not work quite so smoothly as we scale up to problems with larger numbers of p-bits. The system tends to get stuck in metastable states just as in the physical world solids develop defects that keep them from reaching the lowest energy state. Optimization by quantum annealing: An approach that has been explored is the process of quantum annealing using a network of quantum spins implemented with superconducting q-bits 83,84 . However, it is known that for certain classes of quantum problems classified by 'stoquastic' Hamiltonians 85 , a network of q-bits can be approximated with a larger network of p-bits operating in hardware (Fig. 9) 86 . We have made use of this equivalence to design p-circuits whose SPICE simulations show correlations and averages comparable to those obtained with quantum annealers 86 . ## IV. CONCLUSIONS In summary, we have introduced the concept of a probabilistic or p-bit, intermediate between the standard bits of digital electronics and the emerging q-bits of quantum computing. Low barrier magnets or LBM's provide a natural physical representation for p-bits and can be built either from perpendicular magnets (PMA) designed to be close to the in-plane transition or from circular in-plane magnets (IMA). Magnetic tunnel junctions (MTJ) built using LBM's as free layers can be combined with standard NMOS transistors to provide three-terminal building blocks for large scale probabilistic circuits that can be designed to perform useful functions. Interestingly, this three-terminal unit looks just like the 1T/MTJ de- FIG. 9. Mapping a q-bit network into a p-bit network : A special class of quantum many body Hamiltonians that are 'stoquastic' can be solved by mapping them to a classical network of p-bits that consist of a finite number of replicas of the original system that are interacting in the 'vertical' direction. This approach implemented in software is also known as the Path Integral Monte Carlo method. A hardware implementation would constitute a p-computer that is capable of performing quantum annealing 86 . <details> <summary>Image 9 Details</summary>  ### Visual Description \n ## Diagram: Dimensionality Expansion with Bit Arrays ### Overview The image is a diagram illustrating the relationship between a d-dimensional n-bit array and a (d+1)-dimensional p-bit array. It visually represents an expansion of dimensionality achieved through replication. The diagram uses a visual metaphor of arrays of points with arrows to represent the dimensionality and bit representation. ### Components/Axes The diagram consists of two main sections separated by an equals sign ("==="). * **Left Side:** A d-dimensional array represented by orange circles with arrows pointing outwards. Labeled "d - dimensional" and "n - bit array". * **Right Side:** A (d+1)-dimensional array represented by blue arrowheads. This side is composed of 'n' replicas of the d-dimensional array stacked on top of each other. Labeled "(d + 1) - dimensional", "n - replicas", and "p - bit array". * **Arrows:** Curved arrows connect the d-dimensional array to the (d+1)-dimensional array, indicating the replication process. ### Detailed Analysis or Content Details The diagram doesn't contain numerical data points, but it conveys a conceptual relationship. * **Dimensionality:** The left side represents a space with 'd' dimensions, while the right side represents a space with 'd+1' dimensions. * **Bit Representation:** The left side is described as an "n-bit array", and the right side as a "p-bit array". The relationship between 'n' and 'p' is implied through the replication process. * **Replication:** The right side shows 'n' copies (replicas) of the d-dimensional array stacked to create the (d+1)-dimensional array. * **Visual Representation:** The orange circles on the left represent data points in the d-dimensional space, and the arrows indicate the direction or magnitude of some property associated with each point. The blue arrowheads on the right represent the same data points in the expanded (d+1)-dimensional space. ### Key Observations The diagram highlights a method for increasing dimensionality by replicating an existing array. The replication process is visually emphasized by the stacking of the arrays and the curved arrows. The diagram does not provide specific values for 'd', 'n', or 'p', but it establishes a conceptual link between them. ### Interpretation This diagram likely illustrates a concept in machine learning or data representation, specifically related to feature engineering or expanding the feature space. The replication of the d-dimensional array to create the (d+1)-dimensional array suggests a technique for creating new features from existing ones. The 'n-bit array' and 'p-bit array' labels suggest that the dimensionality expansion is also related to the representation of data using bits. The diagram could be illustrating how a lower-dimensional bit array can be expanded into a higher-dimensional bit array through replication, potentially for encoding or processing information. The diagram is a conceptual illustration and does not provide quantitative data. It serves to visually explain a relationship between dimensionality, bit representation, and replication. The equal sign suggests an equivalence or transformation between the two array representations. The diagram is a simplified representation of a potentially complex process, and further context would be needed to fully understand its specific application. </details> vice used in embedded MRAM technology, with only one difference: the use of an LBM for the MTJ free layer. We hope that this concept will help open up new application spaces for this emerging technology. However, a p-bit need not involve an MTJ, any fluctuating resistor could be combined with a transistor to implement it. It may be interesting to look for resistors that can fluctuate faster based on entities like natural and synthetic antiferromagnets 87,88 , for example. The p-bit also provides a conceptual bridge between two active but disjoint fields of research, namely stochastic machine learning and quantum computing. This viewpoint suggests two broad classes of applications for p-bit networks. First, there are the applications that are based on the similarity of a p-bit to the binary stochastic neuron (BSN), a well-known concept in machine learning. Three-terminal p-bits could provide an efficient hardware accelerator for the BSN. Second, there are the applications that are based on the p-bit being like a poor man's q-bit. We are encouraged by the initial demonstrations based on full SPICE simulations that several optimization problems including quantum annealing are amenable to p-bit implementations which can be scaled up at room temperature using existing technology. ## ACKNOWLEDGMENTS S.D. is grateful to Dr. Behtash Behin-Aein for many stimulating discussions leading up to Ref 16 . ## V. REFERENCES - 1 E. Chen, D. Apalkov, Z. Diao, A. Driskill-Smith, D. Druist, D. Lottis, V. Nikitin, X. Tang, S. Watts, S. Wang, S. Wolf, A. W. Ghosh, J. Lu, S. J. Poon, M. Stan, W. Butler, S. Gupta, C. K. A. Mewes, T. Mewes, and P. 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