2302.06457v3

## A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms Shuvro Chowdhury, Andrea Grimaldi, Navid Anjum Aadit, Shaila Niazi, Masoud Mohseni, Shun Kanai, Hideo Ohno, Shunsuke Fukami, Luke Theogarajan, Giovanni Finocchio, Supriyo Datta and Kerem Y. Camsari Abstract -The transistor celebrated its 75 th birthday in 2022. The continued scaling of the transistor defined by Moore's Law continues, albeit at a slower pace. Meanwhile, computing demands and energy consumption required by modern artificial intelligence (AI) algorithms have skyrocketed. As an alternative to scaling transistors for general-purpose computing, the integration of transistors with unconventional technologies has emerged as a promising path for domain-specific computing. In this article, we provide a full-stack review of probabilistic computing with p-bits as a representative example of the energy-efficient and domain-specific computing movement. We argue that p-bits could be used to build energy-efficient probabilistic systems, tailored for probabilistic algorithms and applications. From hardware, architecture, and algorithmic perspectives, we outline the main applications of probabilistic computers ranging from probabilistic machine learning and AI to combinatorial optimization and quantum simulation. Combining emerging nanodevices with the existing CMOS ecosystem will lead to probabilistic computers with orders of magnitude improvements in energy efficiency and probabilistic sampling, potentially unlocking previously unexplored regimes for powerful probabilistic algorithms. Index Terms -domain-specific hardware, machine learning, artificial intelligence, p-bits, p-computers, stochastic magnetic tunnel junctions, spintronics, combinatorial optimization, sampling, quantum simulation ## I. INTRODUCTION T HE slowing down of the Moore era of electronics has coincided with the recent revolution in machine learning and AI algorithms. In the absence of steady transistor scaling and energy improvements, training and maintaining large-scale machine learning models in data centers have become a significant energy concern [1]. The widespread implementation of AI, particularly in industries such as autonomous vehicles [2], is an indication that the energy crisis caused by large-scale machine learning models is not just a data center problem, but a global concern. Efforts of extending the Moore era of electronics by improving conventional transistor technology continue vigorously. Examples of this approach include 3D heterogeneous integration, 2D materials for transistors and interconnects [3], new transistor physics via negative capacitance [4, 5] or This work was supported in part by a U.S. National Science Foundation grant CCF 2106260, the Office of Naval Research Young Investigator grant and the Semiconductor Research Corporation. S.F. acknowledges JST-CREST Grant No. JPMJCR19K3 and MEXT X-NICS Grant No. JPJ011438. S.K. acknowledges JST-PRESTO Grant No. JPMJPR21B2. A. Grimaldi and G. Finocchio are with the Department of Mathematical and Computer Sciences, Physical Sciences and Earth Sciences, University of Messina, Messina, Italy. M. Mohseni is with Google Quantum AI. S. Kanai, H. Ohno, and S. Fukami are with RIEC, CSIS, WPI-AIMR and Graduate School of Engineering, Tohoku University, Sendai, Japan. S. Datta is with Elmore Family School of Electrical and Computer Engineering, Purdue University, IN, USA. S. Chowdhury, N. A. Aadit, S. Niazi, L. Theogarajan, and K. Y. Camsari are with the Department of Electrical and Computer Engineering, University of California Santa Barbara, CA, 93106 USA e-mail: (camsari@ucsb.edu). Fig. 1: bit, p-bit, and qubit : Each column shows a schematic representation of the basic computational units of classical computing (left), probabilistic computing (middle), and quantum computing (right). These are, respectively, the bit, the p-bit, and the qubit. <details> <summary>Image 1 Details</summary>  ### Visual Description ## Diagram: Comparison of Classical, Probabilistic, and Quantum Computing Models ### Overview The image visually contrasts three computational paradigms: classical computing (bits), probabilistic computing (p-bits), and quantum computing (qubits). Each section uses color-coded circles (red for 0, blue for 1) and annotations to illustrate fundamental differences in state representation and behavior. ### Components/Axes 1. **Left Section (Classical Computing)**: - **Label**: "bits" - **Visual Elements**: Two circles (red and blue) with arrows pointing to them. - **Text**: "Either 0 or 1" (binary determinism). - **Computing Type**: "Classical computing" (bold blue text). 2. **Middle Section (Probabilistic Computing)**: - **Label**: "p-bits" - **Visual Elements**: Red and blue circles connected by bidirectional arrows, forming a loop. - **Text**: "Fluctuates between 0 and 1" (probabilistic state transitions). - **Computing Type**: "Probabilistic computing" (bold blue text). 3. **Right Section (Quantum Computing)**: - **Label**: "qubits" - **Visual Elements**: Overlapping red and blue circles with a "+" symbol between them. - **Text**: "Superposition of 0 and 1" (quantum state coexistence). - **Computing Type**: "Quantum computing" (bold blue text). ### Detailed Analysis - **Classical Computing (Bits)**: - Represents binary states (0 or 1) as mutually exclusive, static values. - Arrows indicate fixed, unidirectional assignment of states. - **Probabilistic Computing (P-bits)**: - Depicts states as dynamic, with bidirectional arrows showing transitions between 0 and 1. - The looped arrows suggest probabilistic fluctuations rather than deterministic outcomes. - **Quantum Computing (Qubits)**: - Illustrates superposition via overlapping circles and a "+" symbol, implying simultaneous existence of 0 and 1. - No directional arrows, emphasizing non-classical state behavior. ### Key Observations 1. **State Representation**: - Classical bits are rigidly binary. - P-bits introduce probabilistic transitions but remain binary. - Qubits transcend binary constraints through superposition. 2. **Visual Hierarchy**: - Arrows in p-bits emphasize motion, while qubits use static overlap to denote superposition. - Color coding (red=0, blue=1) is consistent across all sections for clarity. 3. **Abstraction Level**: - Classical: Fundamental digital logic. - Probabilistic: Introduces uncertainty in state determination. - Quantum: Represents probabilistic amplitudes and entanglement. ### Interpretation The diagram underscores the evolution of computational models: - **Classical bits** form the basis of traditional computing, operating on strict binary logic. - **P-bits** extend this by incorporating probabilistic behavior, useful in stochastic systems or Monte Carlo simulations. - **Qubits** represent a paradigm shift, leveraging quantum mechanics to enable parallel processing and exponential computational power for specific problems (e.g., factoring, optimization). The absence of numerical data focuses on conceptual distinctions rather than quantitative metrics. The use of overlapping circles for qubits visually reinforces the non-intuitive nature of quantum states, contrasting with the linear progression from classical to probabilistic models. </details> entirely new approaches using spintronic and magnetoelectric phenomena to build energy-efficient switches [6, 7]. A complementary approach to extending Moore's Law is to augment the existing CMOS ecosystem with emerging, nonsilicon nanotechnologies [8, 9]. One way to achieve this goal is through heterogeneous CMOS + X architectures where X stands for a CMOS-compatible nanotechnology. For example, X can be magnetic, ferroelectric, memristive or photonic systems. We also discuss an example of this complementary approach, the combination of CMOS with magnetic memory technology, purposefully modified to build probabilistic computers. ## II. FULL-STACK VIEW AND ORGANIZATION Research on probabilistic computing with p-bits originated at the device and physics level, first with stable nanomagnets [10], followed by low barrier nanomagnets [11, 12]. In [12], the p-bit was formally defined as a binary stochastic neuron realized in hardware. In both approaches with stable and unstable nanomagnets, the basic idea is to exploit the natural mapping between the intrinsically noisy physics of nanomagnets to the mathematics of general probabilistic algorithms (e.g., Monte Carlo, Markov Chain Monte Carlo). Such a notion of natural computing where physics is matched to computation was clearly laid out by Feynman in his celebrated Simulating Physics with Computers talk [13]. Subsequent work on p-bits defined it as an abstraction between bits and qubits (FIG. 1) with the possibility of different physical implementations. In addition to searching for energy-efficient realizations of single devices, p-bit research has extended to finding efficient architectures (through massive parallelization, sparsification [14] and pipelining [15]) along with the identification of promising application domains. This full-stack research program covering hardware, architecture, algorithms, and applications is similar to the related field of quantum computation where a large degree of interdisciplinary expertise Fig. 2: Applications of probabilistic computing : Potential applications of p-bits are illustrated. The list broadly includes problems in combinatorial optimization, probabilistic machine learning, and quantum simulation. <details> <summary>Image 2 Details</summary>  ### Visual Description ## Diagram: Application domains of probabilistic computing with p-bits ### Overview The diagram illustrates three application domains of probabilistic computing using p-bits: **machine learning & AI**, **combinatorial optimization**, and **quantum simulation**. Each domain is represented with network diagrams, flow arrows, and explanatory text. --- ### Components/Axes #### Machine Learning & AI - **Nodes**: - Blue nodes labeled "visible" and "hidden" (dashed lines indicate connections). - Orange nodes labeled "p-bit network." - **Text**: - "massively parallel true random number generation" (top-left). - "training & inference of energy-based models" (left). - "training & inference networks" (bottom-left, with arrows). #### Combinatorial Optimization - **Nodes**: - Orange nodes forming a graph representation. - **Text**: - "QUBO/Ising machines" (top). - NP problems: Max-SAT, Factorization, Max-Cut, Knapsack (inside an oval). - "graph representation" (arrow from graph to energy minimization). - Energy minimization graph (wavy line with "solution!" bubble). #### Quantum Simulation - **Nodes**: - Red and blue nodes labeled "p-bit network" (top). - Orange nodes labeled "quantum network" (middle). - Blue nodes labeled "neural network ansatz" (bottom). - **Text**: - "quantum Monte Carlo" (right). - "trotterization" (arrow from p-bit network to quantum network). - "machine learning systems" (bottom-right). --- ### Detailed Analysis #### Machine Learning & AI - **Flow**: - Blue "visible" and "hidden" nodes form a network, connected to orange "p-bit network" nodes. - Arrows indicate training/inference processes. - **Key Text**: - "massively parallel true random number generation" suggests p-bits enable scalable randomness for training. - "energy-based models" imply probabilistic inference frameworks. #### Combinatorial Optimization - **Flow**: - Graph representation (orange nodes) maps to energy minimization (wavy line). - Solution identified at the lowest energy point. - **Key Text**: - NP problems (Max-SAT, etc.) are solved via QUBO/Ising machines. - Energy minimization graph shows a non-linear path to the solution. #### Quantum Simulation - **Flow**: - P-bit network (red/blue nodes) undergoes "trotterization" to form a quantum network. - Quantum network connects to "quantum Monte Carlo" and "machine learning systems." - **Key Text**: - "neural network ansatz" bridges quantum and classical ML. --- ### Key Observations 1. **Color Coding**: - Blue nodes: Visible/hidden layers (machine learning). - Orange nodes: P-bit networks (all domains). - Red nodes: Quantum network (quantum simulation). 2. **Flow Direction**: - Arrows indicate progression from p-bit networks to specialized systems (e.g., QUBO machines, quantum Monte Carlo). 3. **Missing Data**: - No numerical values or scales provided (e.g., energy levels, node counts). --- ### Interpretation The diagram positions p-bits as foundational elements for three advanced computing paradigms: 1. **Machine Learning**: P-bits enable energy-based models and parallel randomness, critical for training inference networks. 2. **Combinatorial Optimization**: P-bits map NP problems to energy landscapes, with QUBO/Ising machines finding solutions via minimization. 3. **Quantum Simulation**: P-bits simulate quantum systems through trotterization, linking to quantum Monte Carlo and hybrid quantum-classical ML. The absence of numerical data suggests the diagram emphasizes conceptual relationships over quantitative metrics. The progression from p-bit networks to domain-specific systems highlights their versatility in addressing complex computational challenges. </details> is required to move the field forward (see the related reviews Ref. [16, 17]). The purpose of this paper is to serve as a consolidated summary of recent developments with new results in hardware, architectures, and algorithms. We provide concrete and previously unpublished examples of machine learning and AI, combinatorial optimization, and quantum simulation with p-bits (FIG. 2). ## III. FUNDAMENTALS OF P-COMPUTING A large family of problems (FIG. 2) can be encoded to coupled p-bits evolving according to the following equations [12]: $$\begin{array} { r l r } { m _ { i } } & = } & { s i g n \left [ t a n h ( \beta I _ { i } ) - r _ { [ - 1 , + 1 ] } \right ] } & { ( 1 ) } & { d e s c r i j i n g } \end{array}$$ <!-- formula-not-decoded --> where m i is defined as a bipolar variable ( m ∈ {-1 , +1 } ), r is a uniform random number drawn from the interval [ -1 , 1] , [ W ] is the coupling matrix between the p-bits, β is the inverse temperature and { h } is the bias vector. In physical implementations, it is often more convenient to represent p-bits as binary variables, s i ∈ { 0 , 1 } . A straightforward conversion of Eq. (1) and Eq. (2) is possible using the standard transformation, m → 2 s -1 [18]. As stated, Eq. (1) and Eq. (2) do not place any restrictions on the [ W ] , which may be a symmetric or asymmetric matrix. If an update order of p-bits is specified, these equations take the coupled p-bit system to a well-defined steady-state distribution defined by the eigenvector (with eigenvalue +1 ) of the corresponding Markov matrix [12]. Indeed, in case of Bayesian (belief) networks defined by a directed graph, updating the p-bits from parent nodes to child nodes takes the system to a steady-state distribution corresponding to that obtained from the Bayes' Theorem [19]. If the [ W ] matrix is symmetric, one can define an energy, E , whose negated partial derivative with respect to p-bit m i gives rise to Eq. (2): <!-- formula-not-decoded --> In this case, the steady-state distribution of the network is described by [20]: <!-- formula-not-decoded --> also known as the Boltzmann Law. As such, iterating a network of p-bits described by Eq. (1) and Eq. (2) eventually approximates the Boltzmann distribution which can be useful for probabilistic sampling and optimization. The approximate sampling avoids the intractable problem of exactly calculating Z . Remarkably, for such undirected networks, the steady-state distribution is invariant with respect to the update order of pbits, as long as connected p-bits are not updated at the same time (more on this later). This feature is highly reminiscent of natural systems where asynchronous dynamics make parallel updates highly unlikely and the update order does not change the equilibrium distribution. Indeed, this gives the hardware implementation of asynchronous networks of p-bits massive parallelism and flexibility in design. The energy functional defined by Eq. (3) is often the starting point of discussions in the related field of Ising Machines [21-43] with different implementations (see, Ref. [44] for a comprehensive review). In the case of p-bits, however, we view Eq. (1) and Eq. (2) more fundamental than Eq. (3) because the former can also be used to approximate hard inference on directed networks while the latter always relies on undirected networks. Compared to undirected networks using Ising Machines, work on directed neural networks for Bayesian inference has been relatively scarce, although there are exciting developments [19, 45-50]. Finally, the form of Eq. (3) restricts the type of interactions between p-bits to a linear one since the energy is quadratic. Even though higher-order interactions ( k -local) between pbits are possible [18] (also discussed in the context of Ising machines [51, 52]), such higher-order interactions can always be constructed by combining a standard probabilistic gate set at the cost of extra p-bits. In our view, in the case of electronic implementation with scalable p-bits, trading an increased number of p-bits for simplified interconnect complexity is almost always favorable. That being said, algorithmic advantages and the better representative capabilities of higherorder interactions are actively being explored [51, 53]. ## IV. HARDWARE: PHYSICAL IMPLEMENTATION OF P-BITS A. p-bit The p-bit defined in Eq. (1) describes a tunable and discrete random number generator. Its physical implementation includes a broad range of options from noisy materials to analog and digital CMOS (FIG. 3). The digital CMOS implementations of p-bits often consist of a pseudorandom number generator (PRNG) ( r ), a lookup table for the activation function (tanh), and a threshold to generate a one-bit output. A digital input with a specified fixed point precision (e.g., 10 bits with 1 sign, 6 integers and 3 fractional) provides tunability through the activation function. Digital p-bits have been very useful in prototyping probabilistic computers up to tens of thousands of p-bits [54, 55, 14]. They also serve a useful purpose to illustrate why analog or mixed-signal implementations of pbits with nanodevices are necessary. Even using some of the most advanced field programmable gate arrays (FPGA), the footprint of a digital p-bit is very large: Synthesizing such digital p-bits with pseudo-random number generators (PRNGs) of varying quality of randomness results in tens of thousands of individual transistors. In single FPGAs that do not use timedivision multiplexing of p-bits or off-chip memory, only about 10,000 to 20,000 p-bits with 100,000 weights (sparse graphs with degree 5 to 10) fit, even within high-end devices [14]. On the other hand, using nanodevices such as CMOScompatible stochastic magnetic tunnel junctions (sMTJ), millions of p-bits can be accommodated in single cores due to the scalability achieved by the MRAM technology, exceeding 1Gbit MRAM chips [56, 57]. However, before the stable MTJs can be controllably made stochastic, challenges at the material and device level must be addressed [58, 59] with careful magnet design [60-62]. Different flavors of magnetic p-bits exist [63-66], for a recent review, see Ref. [67]. Unlike synchronous or trial-based stochasticity (e.g., [68]) that re- Fig. 3: Different hardware options for building a probabilistic computer : (Top) Various magnetic implementations of a p-bit. These include both digital (CMOS) and mixed-signal implementations (based on, for example, stochastic magnetic tunnel junction with low barrier magnets). (Bottom) A hybrid of classical and probabilistic computing schemes is shown where the classical computer generates weights and programs the probabilistic computer. The probabilistic computer then generates samples accordingly with high throughput and sends them back to the classical computer for further processing. Like the building blocks of p-bits, the synapse of the probabilistic computer can be designed in several ways, including digital, analog, and a mix of both techniques. <details> <summary>Image 3 Details</summary>  ### Visual Description ## Diagram: Hardware Implementations of Probabilistic Bits and Hybrid Probabilistic-Classical Computer System ### Overview The image presents a comparative analysis of hardware implementations for probabilistic bits (P-bits) and a hybrid system integrating probabilistic and classical computing. It includes three distinct hardware architectures (CMOS-based, SOT-based, STT-based) and a conceptual hybrid system diagram. ### Components/Axes #### Top Section: Hardware Implementations of Probabilistic Bits 1. **CMOS-based Implementation** - **Components**: - PRNG (Pseudo-Random Number Generator) - Activation Function - Comparator (A > B) - Digital Signal Path (labeled "I" for input) - **Key Labels**: - "Digital" (top-left) - "CMOS based" (center-left) 2. **SOT-based Implementation** - **Components**: - Voltage Source (V = V₀/2) - Resistor (R) - Low Barrier Magnet (Δ = 0 kT) - Output Voltage (V_OUT) - **Key Labels**: - "SOT based" (center) - "Mixed-signal" (top-right) 3. **STT-based Implementation** - **Components**: - Voltage Source (V₀) - SMTJ (Spin-Transfer Torque Junction) - Output Voltage (V_OUT) - **Key Labels**: - "STT based" (center-right) #### Bottom Section: Hybrid Probabilistic-Classical Computer 1. **Classical Computer** - **Components**: - Computer Monitor - Server/Workstation (labeled "Classical Computer") - **Data Flow**: - Arrows labeled "Samples" (blue) and "Weights" (orange) pointing to the probabilistic computer. 2. **Probabilistic Computer** - **Components**: - Magnetic Elements (m₁, m_N) - Summation Block (ΣW_j m_j + h) - Output (I = ΣW_j m_j + h) - **Synapse Options**: - Digital - CMOS - Mixed Signal - Resistive Crossbar - Capacitive Crossbar ### Detailed Analysis - **CMOS-based**: Purely digital implementation using PRNG for randomness, activation function for processing, and comparator for decision-making. - **SOT-based**: Mixed-signal analog/digital hybrid using spin-orbit torque (SOT) for probabilistic bit generation, with explicit voltage/resistance parameters (Δ = 0 kT). - **STT-based**: Spin-transfer torque junction (SMTJ) for probabilistic bit manipulation, emphasizing magnetic domain switching. - **Hybrid System**: Classical computer provides samples/weights to probabilistic computer, which processes via magnetic elements and summation logic. Synapse options suggest flexibility in interconnect technology. ### Key Observations 1. **Technology Spectrum**: - CMOS (digital) vs. SOT/STT (analog/magnetic) implementations represent a continuum from digital to analog probabilistic computing. 2. **Hybrid Architecture**: - Classical computer handles deterministic tasks (samples/weights), while probabilistic computer manages stochastic computations (magnetic elements, summation). 3. **Synapse Flexibility**: - Multiple crossbar technologies (resistive/capacitive) indicate adaptability in probabilistic computing hardware. ### Interpretation The diagram illustrates a transition from traditional digital computing (CMOS) to emerging analog/magnetic technologies (SOT/STT) for probabilistic computing. The hybrid system suggests a future where classical and probabilistic computers collaborate, with the probabilistic unit handling uncertainty-driven tasks (e.g., optimization, sampling) while the classical system manages structured data. The explicit labeling of synapse options (resistive/capacitive crossbars) highlights ongoing research into energy-efficient interconnects for such systems. Notably, the absence of numerical performance metrics (e.g., speed, power consumption) leaves the relative efficiency of each implementation open to interpretation, emphasizing conceptual rather than quantitative comparison. </details> quires continuous resetting, the temporal noise of low-barrier nanomagnets makes them ideally suited to build autonomous, physics-inspired probabilistic computers, providing a constant stream of tunably random bits [69]. Following earlier theoretical predictions [70-72], recent breakthroughs in low-barrier magnets have shown great promise, using stochastic MTJs with in-plane anisotropy where fluctuations can be of the order of nanoseconds [73-75]. Such near-zero barrier nanomagnets should be more tolerant to device variations because when the energy-barrier ∆ is low, the usual exponential dependence of fluctuations is much less pronounced. These stochastic MTJs may be used in electrical circuits with a few additional transistors (FIG. 3) to build hardware p-bits. Two flavors of stochastic MTJ-based p-bits were proposed in Ref. [12] (SOT-based) and in Ref. [70] (STT-based). Both of these p-bits have now been experimentally demonstrated in Refs. [18, 76, 77] (STT) and in Ref. [78] (SOT). While many other implementations of p-bits are possible, from molecular nanomagnets [79] to diffusive memristors [80], RRAM [81], perovskite nickelates [82] and others, two additional advantages of the MRAM-based p-bits are the proven manufacturability (up to billion bit densities) and the amplification of room temperature noise. Even with the thermal energy of kT in the environment, magnetic switching causes large resistance fluctuations in MTJs, creating hundreds of millivolts of change in resistive dividers [70]. Typical noise on resistors (or memristors) is limited by the √ kT/C limit which is far lower (millivolts) even at extremely low capacitances ( C ). This feature of stochastic MTJs ensures Fig. 4: Architectures of p-computer : (a) Synchronous Gibbs: all p-bits are updated sequentially. N p-bits need N clock cycles ( NT clk ) to perform a complete sweep, T clk being the clock period. (b) Pseudo-asynchronous Gibbs: a sparse network can be colored into a few disjoint blocks where connected p-bits are assigned a different color. Phase-shifted clocks update the color blocks one after the other. N p-bits need ≈ 1 clock cycle T clk to perform a complete sweep, reducing O( N ) complexity of a sweep to O( 1 ), where we assume the number of colors c N . (c) Truly Asynchronous Gibbs: a hardware p-bit (e.g., a stochastic MTJ-based p-bit) provides an asynchronous and random clock with period 〈 T p-bit 〉 . N p-bits need approximately 1 clock to perform a complete sweep, as long as synapse time is less than the clock on average. No graph coloring or engineered phase shifting is required. <details> <summary>Image 4 Details</summary>  ### Visual Description ## Diagram: Comparison of Gibbs Update Strategies ### Overview The image compares three computational strategies for updating probabilistic bits (p-bits) in a network: 1. **Synchronous Gibbs** (a) 2. **Pseudo-asynchronous Gibbs** (b) 3. **Truly Asynchronous Gibbs** (c) Each section includes network diagrams, timelines, and hardware/software annotations to illustrate update mechanisms and efficiency. --- ### Components/Axes #### (a) Synchronous Gibbs - **Network**: Fully connected nodes labeled "N p-bits" (blue dots). - **Timeline**: - Sequential updates: `update p-bit 1 → update p-bit 2 with updated p-bit 1 → ... → update p-bit N with updated p-bits 1 to N-1`. - Time complexity: `time to update all p-bits = N × T_clk` (horizontal axis labeled `T_clk`). - **Hardware**: No explicit hardware shown. #### (b) Pseudo-asynchronous Gibbs - **Network**: Nodes colored in 5 distinct colors (blue, red, green, orange, purple). - **Timeline**: - Parallel updates by color: - `update all p-bits with color 1 → update all p-bits with color 2 based on updated color 1 p-bits → ... → update all p-bits with color 5 based on updated color 1–4 p-bits`. - Time complexity: `time to update all p-bits = T_clk`. - **Legend**: "5 Colors" (color-coded phases). #### (c) Truly Asynchronous Gibbs - **Network**: Fully connected nodes (no color coding). - **Timeline**: - Uncoordinated updates: Multiple `T_clk` phases with no phase-shifting or graph coloring. - Time complexity: `time to update all p-bits ≈ <T_p-bit>` (average clock period). - **Hardware**: VOD (Voltage-Operated Device) with labeled `p-bit` and `VDD` (power supply). --- ### Detailed Analysis #### (a) Synchronous Gibbs - **Flow**: Strict sequential updates propagate dependencies (e.g., p-bit 2 uses updated p-bit 1). - **Time Complexity**: Linear scaling with `N` (number of p-bits), as each update depends on the prior. #### (b) Pseudo-asynchronous Gibbs - **Flow**: Parallel updates grouped by color, reducing dependency chains. - **Time Complexity**: Constant per phase (`T_clk`), but requires 5 phases for full update. #### (c) Truly Asynchronous Gibbs - **Flow**: No coordination; updates occur independently across phases. - **Hardware**: VOD suggests analog/digital hybrid implementation for faster, less synchronized operations. --- ### Key Observations 1. **Synchronous vs. Pseudo-asynchronous**: - Synchronous has higher latency (`N × T_clk`) but deterministic dependencies. - Pseudo-asynchronous reduces latency to `T_clk` via parallel color-based updates. 2. **Truly Asynchronous**: - Eliminates explicit coordination, relying on hardware (VOD) for faster average updates (`<T_p-bit>`). - No phase-shifting or coloring implies higher concurrency but potential for race conditions. 3. **Hardware Role**: - VOD in (c) implies physical layer optimization for asynchronous operations. --- ### Interpretation - **Efficiency Trade-offs**: - Synchronous ensures correctness at the cost of speed. - Pseudo-asynchronous balances speed and coordination via color-coded phases. - Truly asynchronous prioritizes speed using hardware but risks instability. - **Scalability**: - Synchronous methods become impractical for large `N` due to linear scaling. - Asynchronous strategies (pseudo/truly) are more scalable but require careful hardware/software design. - **Uncertainty**: - `<T_p-bit>` in (c) suggests variability in update times, unlike fixed `T_clk` in (a) and (b). This analysis highlights the tension between computational correctness, speed, and hardware constraints in probabilistic computing architectures. </details> that they do not require explicit amplifiers [83] at each p-bit, which can become prohibitively expensive in terms of area and power consumption. Estimates of sMTJs-based p-bits suggest they can create a random bit using 2 fJ per operation [18]. Recently, a CMOS-compatible single photon avalanche diodebased implementation of p-bits showed similar, amplifierfree operation [84] and the search for the most scalable, energy-efficient hardware p-bit using alternative phenomena continues. ## B. Synapse The second central part of the p-computer architecture is the synapse, denoted by Eq. (2). Much like the hardware p-bit, there are several different implementations of synapses ranging from digital CMOS, analog/mixed-signal CMOS as well as resistive [85] or capacitors crossbars [86, 87]. The synaptic equation looks like the traditional matrix-vector product (MVP) commonly used in ML models today, however, there is a crucial difference: thanks to the discrete p-bit output (0 or 1), the MVP operation is simply an addition over the active neighbors of a given p-bit. This makes the synaptic operation simpler than continuous multiplication and significantly simplifies digital synapses. In analog implementations, the use of in-memory computing techniques through charge accumulation could be useful with the added simplification of digital outputs of p-bits [88, 89]. It is important to note how the p-bit and the neuron for eventually integrated p-bit applications can be mixed and matched, as an example of creatively combining these pieces, see the FPGA-stochastic MTJ combination reported in Ref. [77]. The best combination of scalable p-bits and synapses may lead to energy-efficient and large scale p-computers. At this time, various possibilities exist with different technological maturity. ## V. ARCHITECTURE CONSIDERATIONS ## A. Gibbs sampling with p-bits The dynamical evolution of Eqs. (1-2) relies on an iterated updating scheme where each p-bit is updated one after the other based on a predefined (or random) update order. This iterative scheme is called Gibbs sampling [90, 91]. Virtually all applications discussed in Fig. 2 benefit from accelerating Gibbs sampling, attesting to its generality. In a standard implementation of Gibbs sampling in a synchronous system, p-bits will be updated one by one at every clock cycle as shown in FIG. 4a. It is crucial to ensure that the effective input each p-bit receives through Eq. (2) is computed before the p-bit updates. As such, the T clk has to be longer than the time it takes to compute Eq. (2). In this setting, a graph with N p-bits will require N clock cycles ( NT clk ) to perform a complete sweep where T clk is the clock period. This requirement makes Gibbs sampling a fundamentally serial and slow process. Amuch more effective approach is possible by the following observation: even though updates between connected p-bits need to be sequential, if two p-bits are not directly connected, updating one of them does not directly change the input of the other through Eq. (2). Such p-bits can be updated in parallel without any approximation. Indeed, one motivation of designing restricted Boltzmann machines (RBMs, see Ref. [92]) over unrestricted BMs is to exploit this parallelism: RBMs consist of separate layers (bipartite) that can be updated in parallel. However, this idea can be taken further. If the underlying graph is sparse , it is often easy to split it into disconnected chunks by coloring the graph using a few colors. Even though finding the minimum number of colors is an NP-hard problem [93], heuristic coloring algorithms (such as Dsatur [94]) with polynomial complexity can color the graph very quickly, without necessarily finding a minimum. In this context obtaining the minimum coloring is not critical and sparse graphs typically require a few colors. Such an approach was taken on sparse graphs (with no regular structure) to design a massively parallel implementation of Gibbs sampling in Ref. [14] (FIG. 4b). Connected p-bits are assigned a different color and unconnected p-bits are assigned the same color. Equally phase-shifted and samefrequency clocks update the p-bits in each color block one by one. In this approach, a graph with N p-bits requires only 1 clock cycle ( T clk ) to perform a complete sweep, reducing O( N ) complexity for a full sweep to O (1) , assuming the number of colors is much less than N . Therefore, the key advantage of this approach is that the p-computer becomes faster with larger graphs since probabilistic 'flips per second', a key metric measured by TPU and GPU implementations [95, 96] linearly increases with the number of p-bits. It is important to note that these TPU and GPU implementations also solve Ising problems in sparse graphs, however, their graph degrees are usually restricted to 4 or 6, unlike more irregular and higher degree graphs implemented in Ref. [14]. We term this graph-colored architecture the pseudoasynchronous Gibbs because while it is technically synchronized to out-of-phase clocks, it embodies elements of the truly asynchronous architecture we discuss next. While graph coloring algorithmically increases sampling rates by a factor of N , it still requires a careful design of out-of-phase clocks. A much more radical approach is to design a truly asynchronous Gibbs sampler as shown in FIG. 4c. Here, the idea is to have hardware building blocks with naturally asynchronous dynamics, such as a stochastic magnetic tunnel junction-based p-bit. In such a p-bit, there exists a natural 'clock', 〈 T p-bit 〉 , defined by the average lifetime of a Poisson process [97]. As long as 〈 T p-bit 〉 is not faster than the average synapse time ( t synapse ) to calculate Eq. (2), the network still updates N spins in a single 〈 T p-bit 〉 timescale. This is because the probability of simultaneous updates is extremely low in a Poisson process and further reduced in highly sparse graphs. In fact, preliminary experiments implementing such truly asynchronous p-bits with ring-oscillator activated clocks show that despite making occasional parallel updates, the asynchronous p-computer performs similarly compared to the pseudo-asynchronous system where incorrect updates are avoided with careful phase-shifting [98]. The main appeal of the truly asynchronous Gibbs sampling is the lack of any graph coloring and phase-shift engineering while retaining the same massive parallelism as N p-bits requires approximately a single 〈 T p-bit 〉 to complete a sweep. Given that the FPGAbased p-computers already provide about a 10X improvement in sampling throughput to optimized TPU and GPUs [14], such asynchronous systems are promising in terms of scalability. Stochastic MTJ-based p-bits should be able to reach high densities on a single chip. Around 20 W of projected power consumption can be reached considering 20 µ Wp-bit/synapse combinations at 1M p-bit density [54, 99, 60]. The ultimate scalability of magnetic p-bits is a significant advantage over alternative approaches based on electronic or photonic devices. ## B. Sparsification Both the pseudo-asynchronous and the truly asynchronous parallelism require sparse graphs to work well. The first problem is the number of colors: if the graph is dense, it requires a lot of colors, making the architecture very similar to the standard serial Gibbs sampling. The second problem with a dense graph is the synapse time, t synapse . If many p-bits have a lot of neighbors, the synapse unit needs to compute a large sum before the next update. If the time between two consecutive updates is 〈 T p-bit 〉 , it requires Fig. 5: (a) Original graph of a 3SAT instance uf20-01.cnf [100] having 112 p-bits and a graph density of 6.99%. (Graph density, ρ = 2 | E | / ( | V | 2 -| V | ) where | E | = the number of edges and | V | = the number of vertices in the graph). Some of the p-bits have many local neighbors up to 101 neighbors as shown in the histogram which slows down the synapse and the p-bits need to update slowly. (b) Sparsified graph of the same instance having 410 pbits. COPY gates are inserted between each pair of copies of the same p-bits (COPY edges are highlighted in orange). The graph has a density of 0 . 95% and the maximum number of neighbors is limited to 4 . The synapse operations are now faster and hence the p-bits can be updated faster. Even though the example shown here starts from a low-density graph, the sparsification algorithm we give is general and applicable to any graph. <details> <summary>Image 5 Details</summary>  ### Visual Description ## Network Sparsification Analysis ### Overview The image compares two network structures: an original sparse network and a sparsified version. Both are visualized as interconnected nodes with edge types differentiated by color. Below each network are bar charts showing the distribution of p-bit neighbor counts. The sparsification process increases network density from 6.99% to 95% while significantly expanding the number of p-bits. ### Components/Axes **Network Diagrams:** - **Nodes**: Represent p-bits (processing bits) - **Edges**: - Blue: "Regular" edges (original network) - Orange: "COPY" and "Edge" types (sparsified network) - **Legend Position**: Right side of each diagram - **Density Labels**: - Original: 6.99% (112 p-bits) - Sparsified: 95% (410 p-bits) **Bar Charts:** - **X-axis**: Number of neighbors (1-101 for original, 1-100 for sparsified) - **Y-axis**: Number of p-bits - **Legend**: Blue bars represent p-bit counts - **Sparsified Chart Subcategories**: - 2 neighbors → 1 p-bit - 3 neighbors → 40 p-bits - 4 neighbors → 369 p-bits ### Detailed Analysis **Original Network (a):** - 112 p-bits with 6.99% density - Single dominant bar at 101 neighbors (99.1% of p-bits) - Minimal variation in neighbor counts **Sparsified Network (b):** - 410 p-bits with 95% density - Distributed neighbor counts: - 4 neighbors: 369 p-bits (89.9%) - 3 neighbors: 40 p-bits (9.8%) - 2 neighbors: 1 p-bit (0.2%) - 3.6x increase in total p-bits - 13.6x increase in density **Edge Analysis:** - Original: Predominantly blue "Regular" edges - Sparsified: Orange "Edge" connections dominate - COPY edges appear in sparsified network but lack quantitative data ### Key Observations 1. **Density Transformation**: Sparsification increases density from near-sparse (7%) to near-complete (95%) connectivity 2. **Neighbor Distribution Shift**: - Original: 99.1% of p-bits have maximum neighbors (101) - Sparsified: 89.9% have 4 neighbors, creating a more uniform distribution 3. **Structural Complexity**: Sparsified network shows 3 distinct neighbor groupings vs original's single cluster 4. **Edge Type Evolution**: Introduction of COPY edges in sparsified network suggests replication mechanisms ### Interpretation The sparsification process demonstrates a controlled expansion strategy that: 1. **Enhances Connectivity**: By adding 298 p-bits (266% increase) while maintaining edge integrity 2. **Optimizes Resource Distribution**: Creates a more balanced neighbor topology (4 neighbors as new standard) 3. **Introduces Replication**: COPY edges imply potential for distributed processing or fault tolerance 4. **Reduces Bottlenecks**: Original network's 101-neighbor cluster suggests centralization risks mitigated in sparsified version The data suggests this sparsification technique effectively transforms a sparse, centralized network into a dense, distributed system while maintaining operational efficiency. The 4-neighbor standard in the sparsified network may represent an optimal balance between connectivity and resource utilization. </details> t synapse 〈 T p-bit 〉 to avoid information loss and reach the correct steady-state distribution [101, 54]. However, if the graph is sparse, each p-bit has fewer connections and the updates can be faster without any dropped messages. Any graph can be sparsified using the technique proposed in [14], similar in spirit to the minor-graph embedding (MGE) approach pioneered by D-Wave [102], even though the objective here is to not find an embedding but to sparsify an existing graph. The key idea is to split p-bits into different copies, using ferromagnetic COPY gates. These p-bits distribute the original connections among them, resulting in identical copies with fewer connections. An important point is that the ground-state of the original graph remains unchanged [14], so the method does not involve approximations, unlike other sparsification techniques, for example, based on low-rank approximations [103]. FIG. 5a shows an example of this process where the original graph of a satisfiability (3SAT) instance has been sparsified as shown in FIG. 5b. Irrespective of the input graph size, a sparsified graph has fewer connections locally and thus the neurons hardly ever need to be slowed down. One disadvantage of this technique is the increased number of p-bits, however, the reduced synapse complexity and the possibility of massive parallelization outweigh the costs incurred by additional p-bits, which we consider to be cheap in scaled, nanodevice-based implementations. + <details> <summary>Image 6 Details</summary>  ### Visual Description ## Heatmap Diagram: Optimization Problem Visualizations ### Overview The image presents three distinct optimization problem visualizations (Max-SAT, Number Partitioning, Knapsack) with corresponding mathematical formulations, logic diagrams, and heatmaps. Each section includes probabilistic logic gates, constraint diagrams, and 2D heatmaps with color-coded values. ### Components/Axes #### Mathematical Formulations 1. **Max-SAT** - **Objective**: Maximize ∑ₐ=1^N v_c with v_c = y_c1 ∨ y_c2 ∨ ... ∨ y_cn - **Variables**: v_c ∈ {0,1}, y_x ∈ {0,1} - **Logic Diagram**: Probabilistic OR gates with clamps (missing clauses set to 1). 2. **Number Partitioning** - **Objective**: Minimize |∑ᵢ=1^N s_i n_i| with s_i ∈ {-1, +1} - **Components**: 2-bit adders, sign choice modules, and clamping to 0. 3. **Knapsack** - **Objective**: Maximize ∑ᵢ=1^N v_i x_i subject to ∑ᵢ=1^N w_i x_i ≤ W - **Constraints**: v_i ≥ 0, w_i ≥ 0, x_i ∈ {0,1} - **Logic Diagram**: MAX gates, 2-bit adders, and weight clamping. #### Heatmap Details - **Axes**: - X-axis: Unlabeled (likely represents variable indices or clauses). - Y-axis: Unlabeled (likely represents variable indices or clauses). - **Color Scale**: - Red: -2 (low probability/value) - Blue: +2 (high probability/value) - White: 0 (neutral/undefined). - **Legend**: - Positioned at the bottom of the heatmaps. - Colors: - Red: Probabilistic OR/AND/XOR gates. - Blue: Probabilistic n-bit adder. ### Detailed Analysis #### Max-SAT Heatmap - **Trend**: Diagonal bands of red and blue squares suggest variable dependencies. - **Values**: - Top-left: Red (-2) dominates, indicating low clause satisfaction. - Bottom-right: Blue (+2) appears, suggesting high clause satisfaction. #### Number Partitioning Heatmap - **Trend**: Symmetric red-blue diagonal pattern implies balanced partitioning. - **Values**: - Center: White (0) indicates neutral sums. - Edges: Red (-2) and blue (+2) show extreme imbalances. #### Knapsack Heatmap - **Trend**: Diagonal red-blue gradient reflects trade-offs between value and weight. - **Values**: - Top-right: Blue (+2) indicates high-value, low-weight solutions. - Bottom-left: Red (-2) shows low-value, high-weight solutions. ### Key Observations 1. **Diagonal Patterns**: All heatmaps exhibit diagonal trends, suggesting variable interactions (e.g., clauses, weights, sums). 2. **Clamping Effects**: Logic diagrams show clamps forcing values to 0/1 or MAX, aligning with heatmap extremes. 3. **Color Consistency**: Red (-2) and blue (+2) consistently represent minima/maxima across all heatmaps. ### Interpretation - **Max-SAT**: The heatmap visualizes clause satisfaction probabilities, with red/blue diagonals indicating variable interactions. Clamping ensures all clauses are satisfied (set to 1). - **Number Partitioning**: The symmetric heatmap reflects the challenge of balancing subsets, with clamping to 0 enforcing equality. - **Knapsack**: The gradient highlights the trade-off between maximizing value and minimizing weight, with clamping ensuring constraints are met. - **Uncertainty**: Axis labels are unlabeled, making precise variable indexing ambiguous. The heatmaps lack explicit numerical annotations, relying on color scales for interpretation. ## Conclusion The image demonstrates how probabilistic logic and constraint diagrams map to optimization problems, with heatmaps providing intuitive visualizations of solution distributions. The diagonal patterns and clamping mechanisms are critical for understanding variable dependencies and constraint satisfaction. </details> + + Fig. 6: Invertible logic encoding : The encoding process of three optimization problems, the maximum satisfiability problem (left column), number partitioning (central column), and the knapsack problem (right column), is streamlined and visually summarized into three steps: a problem first has to be condensed into a concise mathematical formulation (upper part of the image); then, an invertible Boolean circuit that topologically maps the problem is conceived; finally, the invertible Boolean circuit is converted into an Ising model using probabilistic AND/OR/NOT gates [14]. ## VI. ALGORITHMS AND APPLICATIONS ## A. Combinatorial Optimization via Invertible Logic When using the Ising model to solve an optimization problem, the first step is to provide a mapping between the Ising model and the problem to be solved. Early work on quantum annealing stimulated by D-Wave's quantum annealers generated a significant amount of useful research in this area [104], some of which are being adopted by quantuminspired classical annealers. There are usually many different ways to find a mapping, for example, some strategies may employ more nodes than others to encode the same instance, while others might result in graphs with topology unsuited to the computational architecture of choice. In this context, the invertible logic approach introduced in Ref. [12] stands out for its flexibility and sparse encodings. The process of mapping an instance into an Ising model can be broadly summarized into three steps, as illustrated by FIG. 6. In the figure, the steps of the invertible logic encoding of three combinatorial optimization problems, maximum satisfiability (left column), number partitioning (middle column), and knapsack (right column), are shown. First, each problem is formalized into a tight mathematical formulation (top row). Next, the problem is mapped into an invertible Boolean logic circuit (central row), meaning that each logic gate can be operated using any terminals as input/output nodes (similar to those discussed in the context of quantum annealing [105, 106] and memcomputing [107, 108]). Finally, the probabilistic circuit is algorithmically encoded into an Ising model (bottom row). Each logic gate has several Ising encodings that map the energy landscape of its logic operator. After the Boolean logic formulation of a problem, this step can be automated in standardized synthesis tools. The overall approach results in relatively sparse circuits, as illustrated in the bottom row of FIG. 6 where all three problems show similarly sparse matrices [W], with bias vectors { h } shown under. The key advantage of this approach, compared to heuristic and dense formulations of Ref. [104], is due to the generality of Boolean logic, quite similar to how present-day digital VLSI circuits are constructed in sparse, hardware-aware networks using billions of transistors. As such, much of the existing ecosystem of high-level synthesis can be directly used to find invertible logic-based encodings for general optimization problems. ## B. Machine Learning: energy-based models Energy-efficient machine learning (ML) with Boltzmann Machines (BMs) is a promising application for probabilistic computers with a recent experimental demonstration in Ref. [76]. Mainstream ML algorithms are designed and chosen with CPU implementation in mind and hence some models are heavily preferred over others even though they are often less powerful. For example, the use of RBMs over the more powerful unrestricted or deep BMs is motivated by the former's efficient software implementation in synchronous systems. However, by exploiting the technique of sparsity and massively parallel architecture described earlier, fast Gibbs sampling with DBMs + + + + + + Fig. 7: Generative neural networks with p-bits : (a) Hybrid computing scheme with probabilistic computer and classical computer is demonstrated where the probabilistic computer generates samples according to the weights given by CPU with a sampling speed of around 100 flips/ns. (b) shows the overview of the learning procedure for the hybrid set-up. Receiving the samples from the probabilistic computer, the CPU computes the gradient, updates the weights and biases, and sends them back to the probabilistic computer until converged. (c) Sparse Deep Boltzmann Machine (DBM) is utilized here as a hardware-aware graph that can be represented with multiple hidden layers of p-bits. Both inter-layer and intra-layer connections are allowed between visible and hidden units. (d) The images shown here are generated with a sparse DBM of 4264 p-bits after training the network with full MNIST. The label p-bits are clamped to a specific image and the network evolves to that image by annealing the system from β = 0 to β = 5 with a step size of 0.125. <details> <summary>Image 7 Details</summary>  ### Visual Description ## Diagram: Hybrid Probabilistic-Classical Computer System for Machine Learning ### Overview The image illustrates a hybrid probabilistic-classical computing architecture for machine learning, combining probabilistic sampling (PC) with classical computation (CPU). It includes workflows for gradient computation, weight optimization, and sparse DBM (Deep Belief Machine) representations, culminating in image generation from the MNIST dataset. --- ### Components/Axes #### (a) Hybrid System Architecture - **Components**: - **Probabilistic Computer (PC)**: Orange box labeled "Probabilistic Computer (PC)". - **Classical Computer (CPU)**: Blue box labeled "Classical Computer (CPU)". - **Data Flow**: - **Samples**: Arrows from PC to CPU (labeled "samples"). - **Weights**: Arrows from CPU to PC (labeled "weights"). - **Label**: "Hybrid Probabilistic - Classical Computer". #### (b) Machine Learning Workflow - **Steps** (blue rounded rectangles): 1. **Get samples from PC**. 2. **Compute gradients (CPU)**. 3. **Compute weights (W) and biases (h) (CPU)**. 4. **Send W and h to PC**. - **Label**: "Overview of machine learning algorithm". #### (c) Sparse DBM Representation - **Structure**: - **Nodes**: - **Input Layer**: Blue nodes labeled "v". - **Hidden Layers**: Orange nodes labeled "h^(1)" and "h^(2)". - **Output Layer**: Yellow nodes (no explicit label). - **Connections**: Fully connected between layers (dashed lines). - **Label**: "Sparse DBM representation with 2-layers of hidden p-bits". #### (d) Image Generation - **Examples**: Four black-and-white pixelated digits (0, 1, 2, 3). - **Caption**: "Image generation with Sparse DBMs: Full MNIST". --- ### Detailed Analysis #### (a) Hybrid System - The PC generates probabilistic samples, which are processed by the CPU to compute gradients and update weights/biases. These updated parameters are then fed back to the PC, creating an iterative optimization loop. #### (b) Workflow - The algorithm alternates between probabilistic sampling (PC) and classical optimization (CPU), typical of contrastive divergence or Gibbs sampling in DBMs. #### (c) Sparse DBM - The 2-layer hidden p-bit architecture reduces computational complexity compared to full DBMs. The sparse connectivity (dashed lines) implies probabilistic dependencies between nodes. #### (d) MNIST Generation - The generated digits demonstrate the system's ability to reconstruct handwritten numerals, validating the effectiveness of the hybrid approach. --- ### Key Observations 1. **Bidirectional Data Flow**: The PC and CPU collaborate iteratively, with samples flowing to the CPU for gradient computation and updated parameters returning to the PC. 2. **Sparse Connectivity**: The DBM's sparse representation (orange/blue/yellow nodes) reduces memory and computational requirements. 3. **MNIST Validation**: The generated digits (0-3) confirm the system's capability for image synthesis. --- ### Interpretation This hybrid architecture leverages the strengths of probabilistic sampling (exploration of high-dimensional spaces) and classical optimization (efficient gradient descent). The sparse DBM representation balances model complexity and computational efficiency, enabling practical deployment on hybrid hardware. The MNIST results suggest the system can generalize to real-world datasets, though scalability to larger images or datasets would require further optimization of the sparse connectivity and sampling strategies. </details> can dramatically improve the state-of-the-art machine learning applications like visual object recognition and generation, speech recognition, autonomous driving, and many more [109]. Here we present an example where a sparse DBM is trained with MNIST handwritten digits (FIG. 7). We randomly distribute the visible and hidden units on the sparse DBM with massively parallel pseudo-asynchronous architecture which yields multiple hidden layers as shown in FIG. 7(c). Contrasting with earlier unconventional computing approaches where the MNIST dataset is reduced to much smaller sizes [110, 111], we show how the full MNIST dataset (60,000 images and no down-sampling) can be trained using p-computers in FPGAs. We use 1200 mini-batches having 50 images in each batch to train the network using the contrastive divergence (CD) algorithm. The process of learning is accomplished using a hybrid probabilistic and classical computer setup. The classical computer computes the gradients and generates new weights while the p-computer generates samples according to those weights (FIG. 7(b)). During the positive phase of sampling, the p-computer operates in its clamped condition under the direct influence of the training samples. In the negative phase, the p-computer is allowed to run freely without any environmental input. After training, the deep network not only can classify images but also generate images. For any given label, the network can create a new sample (not present in the training set) (FIG. 7(d)). This is an important feature of energy-based models and is commonly demonstrated with diffusion models [112]. ## C. Quantum simulation One primary motivation for building quantum computers is to simulate large quantum many-body systems and understand the exotic physics offered by them [113]. Two major challenges with quantum computers are the necessity of using cryogenic operating temperatures and the vulnerability to noise, rendering quantum computers impractical, especially considering practical overheads [114]. Simulating these systems with classical computers is often extremely time-consuming and mostly limited to small systems. One potential application of p-bits is to provide a room-temperature solution to boost the simulation speed and potentially enable the simulation of large-scale quantum systems. Significant progress has been made toward this end in recent years. ## 1) Simulating quantum systems with Trotterization One approach is to build a p-computer enabling the scalable simulation of sign-problem-free quantum systems by accelerating standard Quantum Monte Carlo (QMC) techniques [115]. The basic idea is to replace the qubits in the original lattice with hardware p-bits and replicate the new lattice according to the Suzuki-Trotter transformation [116]. Recently, the convergence time of a 2D square-octagonal qubit lattice initially prepared in a topologically obstructed state was compared among a CPU, a physical quantum annealer [117] and a pcomputer (both digital and analog) [118]. For this particular problem, it was shown that an FPGA-based p-computer emulator can be around 1000 times faster than an optimized C++ (CPU) program. Based on SPICE simulations of a small p-computer, we project that significant further acceleration should be possible with a truly asynchronous implementation. Probabilistic computers can be used for quantum Hamiltonians beyond the usual Transverse Field Ising Model, such as the antiferromagnetic Heisenberg Hamiltonian [119] and even for the emulation of gate-based quantum computers [120]. However, for generic Hamiltonians, (e.g., random circuit sampling), the number of samples required in naive implementations seem to grow exponentially [120] due to the notorious signproblem [121]. However, clever basis transformations [122] might mitigate or cure the sign-problem [123] in the future. ## 2) Machine learning quantum many-body systems With the great success of machine learning and AI algorithms, training stochastic neural networks (such as Boltzmann machines) to approximately solve the quantum many-body problem starting from a variational guess has generated great excitement [124-126] and is considered to be a fruitful combination of quantum physics and machine learning [127]. These algorithms are typically implemented in high-level software programs, allowing users to choose from various network Fig. 8: Machine learning quantum systems with p-bits : (a) Heisenberg Hamiltonian with a transverse field ( Γ = +1 ) is applied to a FM coupled ( J Z = +1 and J xy = +0 . 5 ) linear chain of twelve ( 12 ) qubits with periodic boundary. (b) To obtain the ground state of this quantum system, a restricted Boltzmann machine is employed with 12 visible and 48 hidden nodes, where all nodes in the visible layer are connected to all nodes in the hidden layer. (c) This machine learning model is then embedded onto a hardware amenable sparse p-bit network arranged in a chimera graph using minor graph embedding. We use a coupling strength of 1.0 among the replicated visible and hidden nodes in the embedded p-bit network. (d) An overview of the machine learning algorithm and the division of workload between the probabilistic and classical computers in a hybrid setting is shown. (e) The FPGA emulation of this probabilistic computer performs variational machine learning in tandem with a classical computer, converging to the quantum (exact) result as shown. <details> <summary>Image 8 Details</summary>  ### Visual Description ## Flowchart and Graph: Quantum Ground State Energy Approximation via Machine Learning ### Overview The image depicts a multi-part technical diagram illustrating a machine learning (ML) approach to approximating quantum ground state energy. It includes: 1. A Hamiltonian equation for a spin system (a) 2. A neural network architecture (b) 3. A grid of quantum states (c) 4. A flowchart of the ML algorithm (d) 5. A convergence graph comparing quantum and ML results (e) ### Components/Axes **Hamiltonian Equation (a):** - Equation: H_Q = -Σ J_z σ_i^z σ_{i+1}^z + J_xy (σ_i^x σ_{i+1}^x + σ_i^y σ_{i+1}^y) + L σ_i^x - Variables: J_z (Ising coupling), J_xy (XY coupling), L (transverse field), σ (Pauli matrices) **Neural Network (b):** - Visible layer: 6 green nodes - Hidden layer: 6 pink nodes - Fully connected architecture with bidirectional connections **Quantum State Grid (c):** - 3x3 grid of unit cells - Green nodes: |↑⟩ state - Pink nodes: |↓⟩ state - Dashed lines indicate periodic boundary conditions **Flowchart (d):** 1. Start: Hamiltonian 2. Generate samples from weights {m₁, m₂, ..., m_N} 3. Approximate energy from sampled state 4. Use energy to generate new weights 5. End: Ground state energy and wavefunction **Convergence Graph (e):** - X-axis: Number of iterations (log scale: 10⁰ to 10³) - Y-axis: Energy (range: -18.7 to -18.1) - Legend: - Blue dashed: Quantum (exact) - Orange solid: ML with p-computer ### Detailed Analysis **Graph (e) Trends:** 1. Quantum line (blue dashed) remains constant at ~-18.6 energy 2. ML line (orange solid): - Starts at ~-18.1 (iteration 10⁰) - Rapid decline to ~-18.6 by iteration 10¹ - Converges to quantum value by iteration 10² - Maintains stability at quantum level through 10³ iterations **Flowchart Logic:** - Iterative process: Hamiltonian → Sampling → Energy approximation → Weight update → Convergence - Probabilistic computation enables efficient sampling of quantum states ### Key Observations 1. ML energy converges to quantum ground state within ~100 iterations 2. Initial energy error: ~0.5 units (18.1 vs 18.6) 3. Convergence rate: Exponential decay (log scale x-axis) 4. Final energy accuracy: <0.1 unit difference after convergence ### Interpretation This diagram demonstrates a hybrid quantum-classical approach to solving the ground state problem for spin systems. The ML algorithm effectively approximates quantum mechanical results through: 1. Neural network parameterization of quantum states 2. Probabilistic sampling of spin configurations 3. Energy-based weight updates mimicking quantum annealing The convergence pattern suggests this method could enable: - Efficient quantum state tomography - Variational quantum eigensolver (VQE) implementations - Hybrid quantum-classical optimization - Error mitigation in near-term quantum devices The neural network architecture (b) and quantum state representation (c) indicate a tensor network approach to quantum state approximation, while the flowchart (d) reveals a gradient descent-like optimization process. The graph (e) validates the method's effectiveness, showing exponential convergence typical of variational quantum algorithms. </details> models and sizes according to their needs. However, as with classical machine learning, the difficulty of training strongly hinders the use of deeper and more general models. With scaled p-computers using millions of magnetic p-bits, massively parallel and energy-efficient hardware implementations of the more general unrestricted/deep BMs may become feasible, paving the way to simulate practical quantum systems. To demonstrate one such example of this approach, we show how p-bits laid out in sparse, hardware-aware graphs can be used for machine learning quantum systems (FIG. 8). The objective of this problem is to find the ground state of a many-body quantum system, in this case, a 1D FM Heisenberg Hamiltonian with an external transverse field. We start with an RBM, which is one of the simplest neural network models, and use its functional form as the variational guess for the ground state probabilities (the wavefunction is obtained by taking the square root of probabilities according to the Born rule). A combination of probabilistic sampling and weight updates gradually adjusts the variational guess such that the final guess points to the ground state of the quantum Hamiltonian. Emulating this variational ML approach with pbits requires a few more steps. An RBM network contains allto-all connections between the visible and hidden layers which is not conducive for scalable p-computers because of the large fanout demanded by the all-to-all connectivity. An alternative is to map the RBM onto a sparse graph through minor graph embedding [102]. Using a hybrid setup with fast sampling in a probabilistic computer coupled with a classical computer, the iterative process of sampling and weight updating can then be performed. The key advantage of having a massively parallel and fast sampler is the selection of higher-quality states of the wave function to update the variational guess. FIG. 8 shows an example simulation of how a p-computer learns the ground state of a 1D FM Heisenberg model. The scaling of p-computers using magnetic p-bits may allow much larger implementations of quantum systems in the future. ## D. Outlook: algorithms and applications beyond Despite the large range of applications we discussed in the context of p-bits, much of the sampling algorithms have been either standard MCMC or generic simulated annealing-based approaches. Future possibilities involve more sophisticated sampling and annealing algorithms such as parallel tempering (PT) (see Ref. [128, 129] for some initial investigations). Further improvements to hardware implementation include adaptive versions of PT [130] as well as sophisticated nonequilibrium Monte Carlo (NMC) algorithms [131]. Ideas involving overclocking p-bits such that they violate the t synapse 〈 T p-bit 〉 requirement for further improvement [14] or sharing synaptic operations between p-bits [82] could also be useful. A combination of these ideas with algorithm-architecture-device co-design may lead to orders of magnitude improvement in sampling speeds and quality. In this context, as a sampling throughput metric, increasing flips/ns is an important goal. In addition, solution quality, the possibility of cluster updates or algorithmic techniques also need to be considered carefully. Given the plethora of approaches from multiple communities, we also hope that model problems, benchmarking studies comparing different Ising machines, probabilistic accelerators, physical annealers and dynamical solvers will be performed in the near future from all practitioners, including ourselves. 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