2502.04524v4

# All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices **Authors**: VictoriaClerico, WooseokChoi, TommasoStecconi, FolkertHorst, LauraBégon-Lours, MatteoGaletta, AntonioLa Porta, NikhilGarg, FabienAlibart, Bert JanOffrein, ValeriaBragaglia [1] Donato Francesco Falcone 1] IBM Research - Europe, Rüschlikon, 8803, Zürich, Switzerland 2] Institut Interdisciplinaire d’Innovation Technologique (3IT), Université de Sherbrooke, Sherbrooke, QC J1K 0A5, Quebec, Canada 3] Institute of Electronics, Microelectronics and Nanotechnology (IEMN), Université de Lille, Villeneuve d’Ascq, 59650, France ## Abstract Analog in-memory computing is an emerging paradigm designed to efficiently accelerate deep neural network workloads. Recent advancements have focused on either inference or training acceleration. However, a unified analog in-memory technology platform—capable of on-chip training, weight retention, and long-term inference acceleration—has yet to be reported. This work presents an all-in-one analog AI accelerator, combining these capabilities to enable energy-efficient, continuously adaptable AI systems. The platform leverages an array of analog filamentary conductive-metal-oxide (CMO)/HfO x resistive switching memory cells (ReRAM) integrated into the back-end-of-line (BEOL). The array demonstrates reliable resistive switching with voltage amplitudes below 1.5 V, compatible with advanced technology nodes. The array’s multi-bit capability (over 32 stable states) and low programming noise (down to 10 nS) enable a nearly ideal weight transfer process, more than an order of magnitude better than other memristive technologies. Inference performance is validated through matrix-vector multiplication simulations on a 64×64 array, achieving a root-mean-square error improvement by a factor of 20 at 1 second and 3 at 10 years after programming, compared to state-of-the-art. Training accuracy closely matching the software equivalent is achieved across different datasets. The CMO/HfO x ReRAM technology lays the foundation for efficient analog systems accelerating both inference and training in deep neural networks. keywords: In-memory computing, Analog ReRAM, Deep Neural Networks, Training, Inference ## 1 Introduction Modern computing systems rely on von Neumann architectures, where instructions and data must be transferred between memory and the processing unit to perform computational tasks. This data transfer, particularly recurrent and massive in prominent artificial intelligence (AI)-related workloads, results in significant latency and energy overhead [1]. Digital AI accelerators address this challenge through computational parallelism, bringing memory closer to the processing units, and exploiting application-specific processors [2, 3]. This approach has demonstrated to bring significant improvements in throughput and efficiency for running deep neural networks (DNNs) [4], but the physical separation between memory and compute units persists. Analog in-memory computing (AIMC) [5] is a promising approach to eliminate this separation and so achieve further power and efficiency improvements in deep-learning workloads [6], by enabling some arithmetic and logic operations to be performed directly at the location where the data is stored. By mapping the weights of DNNs onto crossbar arrays of resistive devices and by leveraging Ohm’s and Kirchhoff’s physical laws, matrix-vector multiplications (MVMs)—the most recurrent operation in AI-workloads [7] —are performed in memory with $O(1)$ time complexity [5, 8, 4]. Recent demonstrations of the AIMC paradigm have primarily focused on accelerating the inference step of digitally trained DNNs [9, 10, 11, 12]. However, the increasing computing demands of modern AI models make the training phase orders of magnitude more costly in time and expenses than inference, highlighting the need for efficient hardware acceleration based on the AIMC paradigm. For instance, Gemini 1.0 Ultra required over $5\cdot 10^{25}$ floating-point operations (FLOPs), approximately 100 days, $\mathrm{24\,MW}$ of power, and an estimated cost of 30 million dollars for training [13]. Analog training acceleration imposes even more stringent requirements on resistive devices. In addition to inference (i.e., the forward pass), the back-propagation of errors, gradient computation, and weight update steps must be performed during the learning phase. However, in the digital domain updating the weights of a matrix of size NxN requires $O(N^{2})$ digital operations, leading to a significant drop in efficiency and speed. Beyond the forward pass, the AIMC approach enables acceleration of (1) backward pass through MVMs transposing the inputs and outputs, (2) gradient computation, and (3) the weight update through gradual bidirectional conductance changes upon external stimuli, all with $O(1)$ time complexity. To achieve this, the ideal analog resistive device should exhibit bidirectional, linear, and symmetric conductance updates in response to an open-loop programming pulse scheme (i.e., without the need for verification following each pulse) [4, 14]. Promising technologies include redox-based resistive switching memory (ReRAM) [15, 16], electro-chemical random access memory (ECRAM) [17], and capacitive weight elements [18]. Addressing the various non-idealities of these technologies [19] requires the co-optimization of technology and designated training algorithms. Gokmen et al. [20] proposed an efficient, fully parallel approach that leverages the coincidence of stochastic voltage pulse trains to carry out outer-product calculations and weight updates entirely within memory, in $O(1)$ time complexity. To relax the device symmetry requirements, a novel training algorithm, known as Tiki-Taka, was designed based on this parallel scheme [21]. The primary advantage of the Tiki-Taka approach lies in reduced device symmetry constraints across the entire conductance (G) range, focusing instead on a localized symmetry point where increases and decreases in G are balanced [21]. More recently, the Tiki-Taka version 2 (TTv2) algorithm was demonstrated in hardware [22] on small-scale tasks using optimized analog ReRAM technology in a 6-Transistor-1ReRAM unit cell crossbar array configuration. However, TTv2 faces some convergence issues when the reference conductance is not programmed with high precision [23]. Analog gradient accumulation with dynamic reference (AGAD) learning algorithm (i.e., TTv4) was proposed to overcome the reference conductance limitation, providing enhanced and robust performance [23]. From a technology perspective, the addition of an engineered conductive-metal-oxide (CMO) layer in a conventional HfO x -based ReRAM metal/insulator/metal (M/I/M) stack has been shown to improve switching characteristics in terms of the number of analog states, stochasticity, symmetry point, and endurance, compared to conventional M/I/M technology [24, 25, 26]. However, while CMO/HfO x ReRAM technology has proven to meet all the fundamental device criteria for on-chip training [24], array-level assessment and BEOL integration remain unexplored. Furthermore, although accelerating DNN training using AIMC is more challenging than inference, a unified technology platform capable of performing on-chip training, retaining the weights, and enabling long-term inference acceleration has yet to be reported. This work fills this gap by demonstrating an all-in-one AI accelerator based on CMO/HfO x ReRAM technology, able to perform analog acceleration of both training and long-term inference operations. Such an integrated approach paves the way for highly autonomous, energy-efficient, and continuously adaptable AI systems, opening new paths for real-time learning and inference applications. The flowchart in Fig. 1 a illustrates the all-in-one analog training and inference challenge addressed in this study. To achieve this goal, CMO/HfO x ReRAM devices, integrated into the BEOL of a $\mathrm{130\,nm}$ complementary metal-oxide-semiconductor (CMOS) technology node with copper interconnects (see ”Methods” section ”Device fabrication” for details), are arranged in an array architecture using a 1T1R unit cell. Compared to implementations that use multiple transistors to control the resistive switching, the 1T1R unit cell maximizes memory density, which is crucial for storing large AI models on a single chip. Fig. 1 b shows an image of the all-in-one analog ReRAM-based AI core used in this work, with the corresponding 8x4 array architecture and the schematic of the BEOL integrated 1T1R cells. The CMO/HfO x ReRAM array is first studied in a quasi-static regime by statistically characterizing the devices’ electro-forming step and quasi-static switching response. A physical 3D finite-element model (FEM) is developed to represent the geometry of the conductive filament and analytically describe the charge transport mechanism within these cells. Subsequently, the weight transfer accuracy and conductance relaxation are experimentally characterized on the 8x4 array. These measurements enable the demonstration of the core’s inference capabilities, validated through representative MVM accuracy simulations on a 64×64 array. After demonstrating the MVM accuracy of the CMO/HfO x ReRAM core, analog switching experiments using an open-loop identical pulse scheme demonstrated the suitability of the same core for analog on-chip training acceleration. To assess the training performance, a realistic device model was used in the simulation, accounting for measured characteristics such as non-linear and asymmetric switching behavior, as well as inter- and intra-device variabilities. The training performance was validated using AGAD on fully connected and long short-term memory (LSTM) neural networks, demonstrating scalability from small to large-scale neural networks. <details> <summary>x1.png Details</summary>  ### Visual Description ## Technical Diagram: AIMC Training/Inference Acceleration & Analog ReRAM AI Core ### Overview The image is a composite technical diagram divided into two main panels, labeled **a** and **b**. Panel **a** illustrates the conceptual flow of Analog In-Memory Computing (AIMC) for training and inference acceleration. Panel **b** details the physical implementation of an "All-in-one analog ReRAM-based AI core," showing the chip, its memory array structure, and a detailed cross-section of a single memory cell. ### Components/Axes The diagram contains no traditional chart axes. It is composed of labeled blocks, circuit schematics, and illustrative diagrams. **Panel a: AIMC training and inference acceleration** * **Main Block (Left):** A rounded rectangle with a background image of a circuit board. It contains two sub-sections: * **(1) In-situ Training:** Contains three colored blocks: * Blue: "Forward [F] pass (short term)" * Orange: "Backward [B] pass" * Teal: "Gradient accumulation & Parallel Weight Update" * **(2) In-situ Inference:** Contains one blue block: * "Forward [F] pass (long term)" * **Circuit Diagrams (Right):** Two schematic diagrams connected by lines to the main block, illustrating the electrical operation. * **Top Diagram:** Shows a crossbar array with word lines (V1, V2, V3) and bit lines (I1, I2). Arrows labeled **F** (blue, curved) and **B** (orange, curved) indicate forward and backward pass current flows. * **Bottom Diagram:** Shows a similar crossbar array. A large teal arrow points right, and a smaller teal arrow points up, indicating the direction of weight update operations. **Panel b: All-in-one analog ReRAM-based AI core** * **Chip Photo (Top-Left):** A photograph of a packaged integrated circuit (IC) with a central die. * **Array Diagram (Bottom-Left):** A schematic labeled "BEOL-integrated Analog ReRAM array." It shows a grid of 1T1R (one transistor, one resistor) cells. * **Horizontal Lines:** Labeled as Word Lines: `WL1`, `WL2`, `...`, `WL4`. * **Vertical Lines:** Labeled as Bit Lines (`BL1`, `BL2`, `...`, `BL8`) and Source Lines (`SL1`, `SL2`, `...`, `SL8`). * **Unit Cell Cross-Section (Right):** A detailed 3D diagram labeled "1T1R unit cell." It shows the vertical stack of materials and layers. * **Top Layers (BEOL - Back End Of Line):** From top to bottom: * `BL` (Bit Line) * `SL` (Source Line) * `WL` (Word Line) * **Analog ReRAM stack:** Labeled layers are `TiN` (top electrode), `CMO` (likely a conductive metal oxide), `HfO₂` (hafnium dioxide switching layer), `TiN` (bottom electrode). * **Bottom Layers (FEOL - Front End Of Line):** * `{M2 ... M7}`: Represents intermediate metal layers. * `[M1]`: First metal layer. * **Transistor:** A `130-nm n-MOSFET` with terminals labeled `S` (Source), `G` (Gate), `D` (Drain), and `B` (Body/Bulk). * **Vertical Axis:** An arrow on the right side indicates the vertical progression from FEOL at the bottom to BEOL at the top. ### Detailed Analysis **Panel a - Conceptual Flow:** 1. **In-situ Training Process:** The diagram outlines a three-step training cycle performed directly within the analog memory array: * Step 1: A short-term **Forward [F] pass**. * Step 2: A **Backward [B] pass** for error propagation. * Step 3: **Gradient accumulation & Parallel Weight Update**, where weight adjustments are applied simultaneously across the array. 2. **In-situ Inference Process:** A separate, simpler process for using the trained model: * A long-term **Forward [F] pass** for executing inference tasks. 3. **Circuit Operation:** The accompanying schematics visually map these algorithmic steps to physical current flows (`F`, `B`) and voltage/weight update operations (teal arrows) within the crossbar array hardware. **Panel b - Hardware Implementation:** 1. **Physical Chip:** The top-left photo shows the final packaged product, the "AI core." 2. **Memory Array Architecture:** The bottom-left schematic details how the ReRAM cells are organized in a crossbar structure, addressed by word lines (`WL`) and read/written via bit lines (`BL`) and source lines (`SL`). The `[...]` notation indicates the array extends beyond the shown 4x8 segment. 3. **1T1R Unit Cell Structure:** The right-side cross-section reveals the nanoscale engineering: * The resistive memory element (**Analog ReRAM**) is built in the **BEOL** layers, using a `TiN/CMO/HfO₂/TiN` material stack. * This ReRAM element is connected in series with a selection transistor, a `130-nm n-MOSFET`, built in the **FEOL** silicon layer. * The transistor's gate (`G`) is connected to a word line (`WL`), controlling access to the ReRAM cell. The ReRAM is connected between the bit line (`BL`) and source line (`SL`). ### Key Observations 1. **Tight Integration:** The diagram emphasizes the co-location of compute and memory ("In-situ"), which is the core principle of AIMC, aiming to overcome the von Neumann bottleneck. 2. **Dual-Purpose Hardware:** The same physical ReRAM array is used for both training and inference, with the training process being more complex (involving forward, backward, and update passes). 3. **Standard CMOS Integration:** The use of a `130-nm n-MOSFET` and standard BEOL/FEOL terminology indicates this is designed for integration with conventional silicon CMOS manufacturing processes. 4. **Analog Nature:** The ReRAM is explicitly labeled "Analog," meaning it stores weights as continuous conductance values, not discrete binary states, enabling efficient matrix-vector multiplication. ### Interpretation This diagram illustrates a complete hardware-software co-design for an analog AI accelerator. Panel **a** defines the *what* and *how* of the computational algorithm—performing neural network training and inference directly within memory. Panel **b** reveals the *physical embodiment*—a specialized chip where the fundamental building block is a 1T1R cell that combines a non-volatile analog memory (ReRAM) with a standard transistor. The key technical insight is the **vertical integration** shown in the 1T1R cell. By stacking the analog memory element (BEOL) directly on top of the selection transistor (FEOL), the design achieves high density and efficient electrical access. This architecture enables the parallel operations described in panel **a**, such as the "Parallel Weight Update," where many memory cells can be modified simultaneously by applying appropriate voltages to the word and bit lines. The mention of "130-nm" suggests this is not a cutting-edge process node, implying the design may prioritize cost, reliability, or analog performance characteristics over sheer miniaturization. The overall system aims to dramatically accelerate AI workloads by performing the most computationally intensive operations (matrix multiplications for forward/backward passes) in the analog domain with minimal data movement. </details> Figure 1: All-in-one AIMC challenge. a Schematic representation of the key steps required to perform on-chip training and inference with analog acceleration. Each step is executed using a crossbar array of resistive devices. b CMO/HfO x ReRAM AI core used in this work, consisting of an 8×4 array of 1T1R unit cells. From a fabrication perspective, each ReRAM cell is integrated into the BEOL of a $\mathrm{130\,nm}$ NMOS transistor with copper interconnects. ## 2 Results ### 2.1 Quasi-static array characterization and modelling The quasi-static electrical characterization and analytical transport modelling of the 8x4 CMO/HfO x ReRAM array are presented here. #### 2.1.1 Filament forming Fig. 2 a shows the current-voltage characteristic of the ReRAM devices in the array, undergoing a soft-dielectric breakdown process, commonly referred to as forming [27]. During this step, a quasi-static voltage sweep up to $\mathrm{3.6\,V}$ is applied to the top electrode of each ReRAM device, while grounding the source and driving the gate of the corresponding NMOS selector with a constant $V_{\mathrm{G}}=\mathrm{1.2\,V}$ ensuring current compliance. This process leads to the formation of a highly defect-rich conductive filament in the HfO x layer. Due to the high oxygen vacancy ( $\rm V_{\rm O}^{\rm\cdot\cdot}$ in Kröger–Vink notation [28]) formation energy, ranging from $\mathrm{2.8\,eV}$ to $\mathrm{4.6\,eV}$ in HfO x depending on the stoichiometry [29, 30], defect generation occurs with statistical relevance only during the forming sweep within the HfO x layer [26]. The subsequent application of a negative voltage sweep up to $-1.4\,\mathrm{V}$ , with a constant $V_{\mathrm{G}}=\mathrm{3.3\,V}$ , induces a radial redistribution of the defects within the CMO layer, consistent with findings in literature [26]. This process leads to an increase of the ReRAM conductance and is modelled by considering a constant average radius of the conductive filament, with a local electrical conductivity increase of the CMO layer on top of the filament. Refer to the ”Methods” section ”ReRAM forming modelling” for details. To determine the experimental ReRAM forming voltage, the voltage drop across the NMOS selector must be subtracted from the voltage applied to the 1T1R cell. Fig. 2 b shows the experimental transistor output characteristic, from which the resistance in the triode region at $V_{\mathrm{G}}=\mathrm{1.2\,V}$ is measured and used to extract the distribution of $V_{\mathrm{forming}}^{\mathrm{ReRAM}}$ within the CMO/HfO x ReRAM array (reported in Fig. 2 c). Refer to the ”Methods” section ”ReRAM forming voltage extraction” for details. The highly reproducible CMO/HfO x ReRAM forming step exhibits a 100% yield with a narrow distribution ( $\sigma=\mathrm{75\,mV}$ ) around $V_{\mathrm{forming}}^{\mathrm{ReRAM}}\approx\mathrm{3.2\,V}$ , making it suitable for integration with $\mathrm{130\,nm}$ NMOS transistors rated for $\mathrm{3.3\,V}$ operation. #### 2.1.2 Resistive switching and polarity optimization The underlying physical mechanism behind the resistive switching in analog CMO/HfO x ReRAM devices has been recently unveiled [26, 31, 32]. The current transport is explained by a trap-to-trap tunneling process, and the resistive switching by a modulation of the defect density within the conductive sub-band of the CMO that behaves as electric field and temperature confinement layer. In these works, the analog CMO/HfO x ReRAM device shows a counter-eightwise (C8W) switching polarity, according to the definition proposed in literature [33]. The intrinsically gradual reset (from low to high resistance) process, marked by a temperature decrease, occurs during the positive voltage sweep on the ReRAM top electrode, while the exponential set (from high to low resistance) process, involving a rapid temperature increase, occurs on the negative side [26]. However, when arranged in a 1T1R cell configuration based on an NMOS selector, the C8W switching polarity prevents direct control of the transistor’s $V_{\mathrm{GS}}$ during the exponential set process. This results in reduced switching uniformity, which is critical for the array-level adoption of analog CMO/HfO x ReRAM devices. For this reason, in this work the analog CMO/HfO x ReRAM devices within the 1T1R cells are optimized to exhibit the desirable 8W switching polarity by extending the current switching model in literature [26]. To achieve this, following the positive forming and the initial negative voltage sweep, each device in the array is subjected to a forward and backward voltage sweep from 0 to $-1.5\,\mathrm{V}$ . During this process, oxygen vacancies in the CMO layer radially spread outward, depleting the CMO defect sub-band within a half-spherical volume at the interface with the conductive filament, leading to a reset process (Fig. S3 in Supplementary Information shows the experimental array’s response). Conversely, a voltage sweep from 0 to $1.3\,\mathrm{V}$ enables the migration of oxygen vacancies in the CMO layer in the reverse direction, resulting in a set transition, controlled by the transistor gate. For each 1T1R cell within the 8x4 array, Fig. 2 d shows 5 quasi-static I-V cycling sweeps to experimentally assess the reproducibility of the optimized 8W switching polarity. The electronic transport in both the low-resistive state (LRS) and high-resistive state (HRS) is modelled as a trap-to-trap tunneling process, described by the Mott and Gurney analytical formulation. The physical parameters characterizing the transport in both LRS and HRS ( $N_{\rm e}$ , $\Delta E_{\rm e}$ , $a_{\rm e}$ , $\sigma_{\rm CMO}$ and $r_{\rm CF}$ ) are shown in Fig. 2 d. Refer to the ”Methods” section ”Analytical ReRAM transport modelling” for details on the LRS and HRS modelling. Fig. 2 e illustrates the cumulative probability distribution of the experimental LRS and HRS within the array, demonstrating device-to-device uniformity and a resistance ratio HRS/LRS of approximately 15, with absolute switching voltages $\leq\mathrm{1.5\,V}$ . The excellent uniformity of the forming and the optimized 8W-cycling characteristics set the groundwork for AIMC-based inference and training AI-accelerators using the CMO/HfO x ReRAM technology. <details> <summary>x2.png Details</summary>  ### Visual Description ## Multi-Panel Technical Figure: CMO/HfOₓ ReRAM Array Characterization ### Overview This image is a composite figure containing five subplots (labeled **a** through **e**) that present electrical characterization data and modeling results for a CMO/HfOₓ Resistive Random-Access Memory (ReRAM) array integrated with a transistor (1T1R structure). The data covers the initial forming process, transistor characteristics, cycling behavior, and statistical distributions of key parameters. ### Components/Axes The figure is divided into five distinct panels: * **Panel a (Top Left):** A current-voltage (I-V) plot titled "CMO/HfOₓ ReRAM array forming and modelling". * **Panel b (Top Right):** A transistor output characteristic plot. * **Panel c (Middle Right):** A probability density plot titled "Array forming distribution". * **Panel d (Bottom Left):** A current-voltage (I-V) plot titled "Array quasi-static cycling and modelling". * **Panel e (Bottom Right):** A cumulative probability plot titled "Array HRS-LRS distributions". ### Detailed Analysis #### **Panel a: CMO/HfOₓ ReRAM array forming and modelling** * **Chart Type:** Current-Voltage (I-V) characteristic on a semi-logarithmic scale. * **Axes:** * **Y-axis:** `Current_1T1R [A]` (log scale, ranging from 10⁻⁹ to 10⁻³ A). * **X-axis:** `Voltage_1T1R [V]` (linear scale, ranging from -1.4 to 3.6 V). * **Data Series & Legend:** * Multiple colored lines represent I-V curves for different devices. * A vertical color bar on the right, labeled `Devices`, maps line color to device number (1 to 32). Yellow/green lines correspond to higher device numbers, blue/purple to lower numbers. * **Annotations & Insets:** * A text box in the upper right states `V_G = 1.2 V`, indicating the gate voltage applied to the transistor during measurement. * Two schematic insets depict the device structure (TiN/CMO/HfOₓ/TiN) before and after forming. * **Left Inset (Pre-forming):** Labeled with parameters `σ_CMO = 37 S/cm` and `r_CF = 11 nm`. It shows a narrow conductive filament (CF) beginning to form in the HfOₓ layer. * **Right Inset (Post-forming):** Labeled with parameters `σ_CMO = 5 S/cm` and `r_CF = 11 nm`. It shows a wider conductive filament (`2r_CF`). * Black arrows labeled `①` and `②` indicate the direction of the voltage sweep during the forming process (from 0V to positive voltage, then back). * Two gray circles highlight regions of interest on the curves, likely indicating the onset of forming and the high-current state. * **Trend:** All devices show a sharp increase in current (forming event) at a positive voltage between approximately 2.5V and 3.5V. The current then saturates at a high level (~10⁻³ A) as the voltage is swept back. #### **Panel b: Transistor output characteristic** * **Chart Type:** Family of curves for a transistor. * **Axes:** * **Y-axis:** `I_DS [mA]` (linear scale, 0 to 3 mA). * **X-axis:** `V_DS [V]` (linear scale, 0 to 4 V). * **Data Series & Legend:** * Multiple lines, color-coded by gate voltage (`V_G`). * A vertical color bar on the right, labeled `V_G [V]`, maps line color to gate voltage (0V to 3V). Blue lines are low V_G, red lines are high V_G. * **Trend:** For a fixed V_G, drain-source current (`I_DS`) increases with `V_DS` and then saturates. For a fixed `V_DS`, `I_DS` increases significantly with increasing `V_G`. #### **Panel c: Array forming distribution** * **Chart Type:** Normalized probability density function (histogram with fitted curve). * **Axes:** * **Y-axis:** `Normalized Probability Density` (linear scale, 0.0 to 1.0). * **X-axis:** `V_forming^ReRAM [V]` (linear scale, ~2.9V to 3.4V). * **Data Series & Legend:** * Green dots (`Exp.`) represent experimental data points for the forming voltage of individual devices. * A dashed vertical line marks the mean forming voltage at `3.17 V`. * A solid green curve represents a Gaussian fit to the data. * **Annotations:** * A text box indicates the standard deviation: `±σ = 75 mV`. * **Distribution:** The forming voltages are normally distributed around a mean of 3.17V with a standard deviation of 75mV. #### **Panel d: Array quasi-static cycling and modelling** * **Chart Type:** Current-Voltage (I-V) characteristic on a semi-logarithmic scale. * **Axes:** * **Y-axis:** `Current_1T1R [A]` (log scale, 10⁻⁷ to 10⁻⁴ A). * **X-axis:** `Voltage_1T1R [V]` (linear scale, -1.5V to 1.3V). * **Data Series & Legend:** * A legend in the top center identifies: * `32Dev. 5Cy. each`: Blue lines represent experimental I-V data from 32 devices, each cycled 5 times. * `Model`: A yellow dashed line represents the simulation/model fit. * **Annotations & Insets:** * Two schematic insets depict the device structure in Low Resistance State (LRS) and High Resistance State (HRS). * **Left Inset (LRS):** Lists parameters: `N_LRS = 5·10¹⁹ cm⁻³`, `ΔE_LRS = 65 meV`, `a_LRS = 2.1 nm`, `σ_CMO = 9 S/cm`, `r_CF = 11 nm`. * **Right Inset (HRS):** Lists parameters: `N_HRS = 1.2·10¹⁸ cm⁻³`, `ΔE_HRS = 80 meV`, `a_HRS = 3.6 nm`, `σ_CMO = 0.45 S/cm`, `r_CF = 11 nm`. * Black arrows indicate the bipolar switching direction: positive voltage for SET (HRS to LRS), negative voltage for RESET (LRS to HRS). * Gray circles highlight the SET and RESET transition regions on the curves. * **Trend:** The device exhibits clear bipolar resistive switching. The model (yellow dashed line) closely follows the average behavior of the experimental data (blue lines). #### **Panel e: Array HRS-LRS distributions** * **Chart Type:** Cumulative probability plot. * **Axes:** * **Y-axis:** `Cumulative Probability [%]` (linear scale, 2% to 95%). * **X-axis:** `Resistance [Ω]` (log scale, 10⁴ to ~5·10⁵ Ω). * **Data Series & Legend:** * A legend identifies: * `HRS`: Blue dots. * `LRS`: Red dots. * `Mean`: Dashed vertical lines. * **Annotations:** * Text boxes provide statistical parameters for each state: * **LRS (Red):** `μ = 18 kΩ`, `σ/μ = 0.25`. * **HRS (Blue):** `μ = 256 kΩ`, `σ/μ = 0.25`. * A label at the bottom states `read @ +0.2 V`, indicating the resistance was measured at a read voltage of 0.2V. * **Distribution:** The LRS and HRS resistance values form two distinct, well-separated distributions. Both have a relative standard deviation (σ/μ) of 0.25, indicating similar variability. The HRS mean is approximately 14 times higher than the LRS mean. ### Key Observations 1. **Forming Process (Panel a & c):** The initial electroforming of the ReRAM devices is a stochastic process with a relatively tight distribution (σ = 75 mV around 3.17 V). 2. **Transistor Control (Panel b):** The transistor provides effective current compliance and control, as seen by the well-behaved output characteristics. 3. **Bipolar Switching (Panel d):** The devices exhibit robust and repeatable bipolar switching behavior over multiple cycles, which is well-captured by the physical model. 4. **State Separation (Panel e):** There is a clear and significant resistance window between the HRS (~256 kΩ) and LRS (~18 kΩ), which is crucial for memory readout. The variability (σ/μ = 0.25) is consistent across both states. 5. **Model Agreement (Panel d):** The physical model, using parameters related to oxygen vacancy concentration (`N`), activation energy (`ΔE`), and filament geometry (`a`, `r_CF`), accurately reproduces the experimental switching curves. ### Interpretation This figure provides a comprehensive electrical and physical analysis of a CMO/HfOₓ ReRAM array. The data demonstrates the fundamental functionality of the memory cells: a one-time forming step creates a conductive filament, after which the device can be reliably switched between a high and low resistance state using bipolar voltage pulses. The **forming distribution (c)** is critical for circuit design, as it defines the voltage margin required to initialize all cells in an array. The **transistor characteristics (b)** confirm its suitability as a selection and current-limiting element. The **cycling data and model (d)** reveal the underlying physics of switching, linking electrical behavior to changes in the conductive filament's properties (e.g., vacancy concentration and effective radius). Finally, the **resistance distributions (e)** quantify the memory window and variability, which are key metrics for determining the reliability and potential density of a memory technology. The consistent relative variability (σ/μ) in both states suggests a common physical origin for the fluctuations, likely related to the atomic-scale nature of the conductive filament. </details> Figure 2: ReRAM array quasi-static electrical characterization and modelling. a (1) Experimental positive forming sweeps (with $V_{\mathrm{G}}=\mathrm{1.2\,V}$ ) of the 8x4 CMO/HfO x ReRAM devices in the array. This process results in an average filament radius of $11\,\mathrm{nm}$ in the HfO x layer. (2) Negative voltage sweeps (with $V_{\mathrm{G}}=\mathrm{3.3\,V}$ ) to enable defect redistribution within the CMO layer, resulting in an increase in the conductance of the ReRAM cells. A representative sweep is shown in black. The insets illustrate a schematic representation of the defect arrangement within the stack. b Experimental NMOS transistor output characteristic, with $V_{\mathrm{G}}$ up to $\mathrm{3\,V}$ . c Experimental ReRAM forming voltage distribution measured from the CMO/HfO x ReRAM array. The experimental data used to extract the distribution are represented as green points. d Superposition of 5 I-V quasi-static 8W-cycles (in blue) for each of the 32 devices in the array, using $V_{\mathrm{set}}=\mathrm{1.3\,V}$ , $V_{\mathrm{G}}=\mathrm{1.1\,V}$ and $V_{\mathrm{reset}}=\mathrm{-1.5\,V}$ , $V_{\mathrm{G}}=\mathrm{3.3\,V}$ for set and reset processes, respectively. The analytical trap-to-trap tunneling model effectively captures the electron transport in both the LRS and HRS (yellow dashed lines). The physical parameters characterizing the transport, extracted from the model, and a schematic representation of the defect distribution, are presented for both resistive states. e Cumulative probability distributions for both LRS and HRS. For each array cell, the average resistance over 5 I-V cycles in LRS and HRS is defined at a read voltage of $\mathrm{0.2\,V}$ . ### 2.2 Analog inference with CMO/HfO x ReRAM core Here, the experimental characterization of the key metrics of the CMO/HfO x ReRAM array relevant to inference performance is presented. Specifically, the continuous conductance tuning capability is demonstrated over a range spanning approximately one order of magnitude. The trade-off between weight transfer programming noise of CMO/HfO x ReRAM devices and number of required iterations for programming convergence is analyzed across different acceptance ranges. Furthermore, conductance relaxation—defined as the change in conductance over time after programming—is characterized. Finally, the combined impact of weight transfer, conductance relaxation, limited input/output quantization of the digital-to-analog converter (DAC) and analog-to-digital converter (ADC), and IR drop on the array wires is evaluated with respect to MVM accuracy. #### 2.2.1 Weight transfer accuracy In memristor-based AIMC inference accelerators, pre-trained normalized weights are initially mapped into target conductances and subsequently programmed into hardware in an iterative process known as weight transfer. This iterative process, which stops once the programmed conductance converges to the target value within a defined acceptance range, inherently introduces an error due to the analog nature of conductance weights. This error, described by a normal distribution with the standard deviation referred to as programming noise ( $\sigma_{\rm prog}$ ), leads to a drop in MVM accuracy. To quantify this non-ideality, the non-volatile multi-level capability of the CMO/HfO x ReRAM array is characterized. Fig. 3 a shows the experimental cumulative distribution of conductance values for 35 representative levels, with all states sharply separated and without any overlap. Fig. 3 b shows a schematic representation of the closed-loop (i.e., program-verify) scheme, where identical set and reset pulse trains are employed to program each ReRAM cell to its target conductance within a desired acceptance range (see ”Methods” section ”Identical-pulse closed-loop scheme” for details). Selecting programming conditions involves a fundamental trade-off: a narrower acceptance range can improve programming precision by reducing programming noise, but it increases the number of iterations required for convergence (see Fig. 3 d). Besides the longer programming time, other non-idealities to consider when choosing the acceptance range are (1) the conductance relaxation immediately after programming, which is characterized in 2.2.2 for CMO/HfO x ReRAM devices, and (2) read noise, which has already been characterized between 0.2% and 2% of G target for CMO/HfO x ReRAM devices [25] within a similar conductance range used in this work. The trade-off between the programming noise and the number of iterations is characterized for two representative acceptance range intervals: 0.2% and 2% of G target, respectively. Fig. 3 c illustrates the experimental number of pulses needed to converge to the G target using the two representative acceptance ranges. On average, each cell requires approximately 11 and 89 set / reset pulses for acceptance ranges of 2% and 0.2% of G target, respectively. Since the acceptance range is defined as a percentage of G target, the number of iterations required for convergence is almost independent of the target conductance value. In the Supplementary Information, Fig. S5 a shows the experimental cumulative distribution of conductance values for the same 35 representative levels presented in Fig. 3 a, but using 2% G target as acceptance range. The standard deviation of the representative conductance levels is extracted and fitted as a linear function of the target conductance (dashed lines), as shown in Fig. 3 e, for both acceptance ranges. For all conductance levels, a standard deviation of less than 0.1 µS (1 µS) is achieved considering 0.2% G target (2% G target) as the acceptance range. This is more than one order of magnitude lower compared to other memristive technologies, such as phase-change memory (PCM) arrays, targeting similar conductance ranges [34, 35, 36]. These results demonstrate that CMO/HfO x ReRAM cells achieve an almost ideal weight transfer during programming, enabling the distinction of more than 32 states (5 bits). <details> <summary>x3.png Details</summary>  ### Visual Description ## [Multi-Panel Technical Figure]: CMO-HfOx ReRAM Programming Analysis ### Overview This composite figure presents a technical analysis of programming a CMO-HfOx Resistive Random-Access Memory (ReRAM) device using a closed-loop, identical-pulse scheme. It includes a conductance state distribution map, a schematic of the programming protocol, and three plots analyzing the relationship between programming iterations, target conductance, and programming noise (σ_prog) under different acceptance ranges. ### Components/Axes The figure is divided into five panels labeled **a** through **e**. **Panel a: CMO-HfOx ReRAM during programming** * **Type:** 2D Heatmap / Scatter Plot. * **X-axis:** "Target Conductance [µS]". Linear scale from 10 to 90 µS, with major ticks every 10 µS. * **Y-axis:** "Cumulative Distribution Function". Linear scale from 0.00 to 1.00, with major ticks every 0.25. * **Color Bar (Right):** Labeled "States". A vertical gradient from blue (bottom, value 1) to red (top, value 35). Major ticks at 1, 8, 16, 32, 35. * **Legend/Annotation:** A text box in the upper portion reads: "Acceptance Range: 0.2% G_target". * **Data Representation:** A grid of colored dots. Each column corresponds to a specific target conductance (G_target). The color of the dots in a column indicates the number of discrete conductance states (from 1 to 35) achieved for that target. The vertical spread (CDF) shows the distribution of programmed states. **Panel b: Identical-pulse closed-loop scheme** * **Type:** Two aligned schematic diagrams. * **Top Graph (Voltage vs. Time):** * **Y-axis:** "V [a.u.]" (arbitrary units). Labels: "V_set" (positive red pulses), "V_read" (smaller grey pulses), "V_reset" (negative blue pulses). * **X-axis:** "time [a.u.]". * **Flow:** Shows a sequence: a V_set pulse, followed by a V_read pulse, repeated multiple times (indicated by "..."), then a V_reset pulse, followed by a V_read pulse, and so on. * **Bottom Graph (Conductance vs. Time):** * **Y-axis:** "G [a.u.]". A horizontal green dashed line is labeled "G_target". Two horizontal black dotted lines above and below it define the "±Acc. Range". * **X-axis:** "time [a.u.]". Aligned with the top graph. * **Data Representation:** Circles represent measured conductance after each pulse. The circles change color from blue to green as they approach G_target. The final circle is solid green, within the acceptance range. **Panel c: Iterations vs G_target** * **Type:** Scatter Plot with overlaid trend lines. * **X-axis:** "Target Conductance [µS]". Linear scale from 10 to 90 µS. * **Y-axis:** "Closed-loop iterations". Logarithmic scale from 10^0 (1) to 10^2 (100). * **Legend (Top):** Two colored boxes: "Acc. Range 0.2%" (purple) and "Acc. Range 2%" (yellow-green). * **Legend (Bottom):** "Iterations" (small dots), "Avg per G" (solid line with circle markers), "---Avg" (dashed line). * **Data Series:** 1. **Purple dots/line (0.2% range):** Data points are scattered between ~10 and ~100 iterations. The average line ("Avg per G") fluctuates around 80-90 iterations. A horizontal dashed line labeled "89" indicates the overall average. 2. **Yellow-green dots/line (2% range):** Data points are scattered between ~1 and ~20 iterations. The average line fluctuates around 10-15 iterations. A horizontal dashed line labeled "11" indicates the overall average. **Panel d: Prog. noise vs iterations** * **Type:** 2D Heatmap / Contour Plot. * **X-axis:** "Closed-loop iterations". Labeled "Low" to "High". * **Y-axis:** "σ_prog" (Programming noise). Labeled "Low" to "High". * **Color Bar (Right):** Labeled "Acc. Range". Scale from 0.2 (blue) to 2% (yellow). * **Annotations:** * A white double-headed arrow labeled "Trade-off" runs diagonally from the bottom-left (low iterations, low noise) to the top-right (high iterations, high noise). * **Top-left (High noise, Low iterations):** A white 'X' and text box: "σ_prog ∈ [0.1, 1]µS, Iterations ≈ 10". * **Bottom-right (Low noise, High iterations):** A white 'X' and text box: "σ_prog ∈ [0.01, 0.1]µS, Iterations ≈ 90". **Panel e: Prog. noise vs G_target** * **Type:** Scatter Plot with fitted power-law curves. * **X-axis:** "Target Conductance [µS]". Linear scale from 10 to 90 µS. * **Y-axis:** "σ_prog [µS]". Logarithmic scale from 10^-2 (0.01) to 10^0 (1). * **Legend (Top):** Same as Panel c: "Acc. Range 0.2%" (purple) and "Acc. Range 2%" (yellow-green). * **Data Series & Equations:** 1. **Purple dots (0.2% range):** Data points follow an upward trend. A fitted curve is annotated with the equation: `σ_prog = 10^-3 * (1.1 * G + 0.8)`. 2. **Yellow-green dots (2% range):** Data points follow a steeper upward trend. A fitted curve is annotated with the equation: `σ_prog = 10^-3 * (11.3 * G + 11.2)`. ### Detailed Analysis * **Panel a:** Shows that for a given target conductance (G_target), the programming process can settle into one of many discrete states (1-35). The color gradient indicates that higher target conductances (right side, ~70-90 µS) are associated with a higher number of possible states (red, ~32-35), while lower targets (left side, ~10-30 µS) are associated with fewer states (blue, ~1-16). The CDF shows the probability distribution across these states for each G_target. * **Panel b:** Illustrates the feedback control loop. A set pulse (V_set) is applied, the conductance is read (V_read), and this is repeated until the measured conductance (G) falls within the predefined acceptance range (±Acc. Range) around the target (G_target). Reset pulses (V_reset) are interspersed, likely to prevent saturation or for device conditioning. * **Panel c:** Demonstrates a clear trade-off. Achieving a tighter acceptance range (0.2%) requires significantly more programming iterations (average ~89) compared to a looser range (2%, average ~11). The number of iterations is relatively constant across the range of target conductances (10-90 µS) for a given acceptance range, though with considerable scatter. * **Panel d:** Conceptualizes the fundamental trade-off between programming precision (low σ_prog) and speed (low iterations). High precision (low noise) demands many iterations, while fast programming (few iterations) results in higher noise. The color indicates that the 0.2% acceptance range (blue) corresponds to the high-iteration, low-noise regime, while the 2% range (yellow) corresponds to the low-iteration, high-noise regime. * **Panel e:** Quantifies the relationship between programming noise and target conductance. For both acceptance ranges, σ_prog increases linearly with G_target (on a log-linear plot, indicating a power-law relationship). The slope is much steeper for the 2% acceptance range (coefficient 11.3) than for the 0.2% range (coefficient 1.1), meaning noise worsens more rapidly with increasing conductance when the precision requirement is relaxed. ### Key Observations 1. **Discrete States:** The ReRAM device programs into a finite number of discrete conductance states, not a continuous range. 2. **Precision-Speed Trade-off:** There is an inverse relationship between programming precision (acceptance range/noise) and programming speed (iterations). This is explicitly highlighted in Panel d. 3. **Noise Scaling:** Programming noise (σ_prog) scales linearly with the target conductance value. The scaling factor is heavily dependent on the required precision (acceptance range). 4. **Iteration Consistency:** The number of iterations required to reach a target is largely independent of the target conductance value itself for a fixed acceptance range (Panel c), but the resulting noise is not (Panel e). ### Interpretation This figure characterizes the performance and fundamental limits of a specific closed-loop programming algorithm for CMO-HfOx ReRAM. The data suggests that: * **For applications requiring high precision (e.g., analog computing weights):** One must use a tight acceptance range (0.2%), which will result in slower programming (~89 iterations) but lower absolute noise levels, especially at lower conductance values. * **For applications prioritizing speed (e.g., digital memory):** A looser acceptance range (2%) can be used, enabling much faster programming (~11 iterations), but at the cost of higher conductance variability (noise), which scales poorly with increasing conductance. * **Device Physics Insight:** The linear scaling of σ_prog with G_target (Panel e) may reflect underlying physical mechanisms in the ReRAM filament formation/modulation, where achieving higher conductance states inherently involves more variability. The fitted equations provide a predictive model for noise based on target conductance and desired precision. * **System Design Implication:** The clear trade-off (Panel d) presents a design knob for system architects. They can choose an operating point on the precision-speed curve based on the specific requirements of the neural network or computing task being implemented on the ReRAM array. The data in Panels c and e provide the quantitative basis for making that choice. </details> Figure 3: Weight transfer characterization. a Cumulative distributions of 35 conductance states obtained using an identical-pulse closed-loop scheme with a 0.2% G target acceptance range. For each distribution, the entire CMO/HfO x ReRAM array was programmed to the corresponding G target, and the conductance values measured during the final closed-loop iteration (during programming) is reported. Each dot represents a 1T1R cell. b An example sequence of the identical-pulse closed-loop programming scheme utilized in this work. c Experimental number of closed-loop iterations as a function of G target for the two representative acceptance ranges. Each semitransparent point represents a 1T1R cell, the opaque points represent the average number of iterations per G target, and the horizontal dashed line indicates the overall average of the opaque points. d Graphical representation of the trade-off between programming noise and the number of iterations required for convergence, as a function of the acceptance range. e Experimental programming noise as a function of G target for the two representative acceptance ranges. Each point represents the standard deviation of the normal distribution measured across the entire array. The dashed lines in black indicate the corresponding linear fits. #### 2.2.2 Conductance relaxation and matrix-vector multiplication accuracy In addition to the excellent weight transfer accuracy during programming as presented in the previous section, the characterization of temporal conductance relaxation is critical to estimate the MVM accuracy over time. In analog ReRAM devices, a significant conductance relaxation has been observed immediately after programming (within 1 second) [9]. Following this initial abrupt conductance change, the relaxation process slows considerably [37, 9]. The physical cause of retention degradation is attributed to the Brownian motion of defects in the resistive switching layer [37]. In this section, the conductance relaxation of the CMO/HfO x ReRAM array after programming is characterized. Fig. 4 a shows the relaxation of the distributions previously reported in Fig. 3 a, approximately 10 minutes after programming. The 35 levels remain distinguishable 10 minutes after programming, with an average overlap of 9.6% between adjacent states gaussians, while the average standard deviation of the distributions increases to 0.6 µS, showing almost independence from the G target (see Fig. 4 b). The stability of the CMO/HfO x ReRAM conductance states is further assessed on a longer time-scale, up to 1 hour. To achieve so, a linearly spaced G target vector within the experimental conductance range of 10 µS to 90 µS is defined, with a fine step of 0.2 µS (400 points). Each G target value is programmed into a single ReRAM device within the array. Due to the size mismatch between the array (32 devices) and the G target vector (size 400), multiple measurement batches are needed. Fig. 4 c shows the experimental relaxation of the 400 programmed states within the entire conductance window, 1 second and 1 hour after programming, executed with the closed-loop scheme (see ”Methods” section ”Identical-pulse closed-loop scheme” for details) and with a 0.2% G target acceptance range. The exhibited conductance error induced by the relaxation process after 1 hour, computed as $G_{\mathrm{1h}}-G_{\mathrm{prog.}}$ , is plotted as a function of the programmed conductances in Fig. 4 d. After 1 hour, although both positive and negative relaxation errors are recorded, an average decrease in conductance is observed across all programmed states, with a relaxation error averaging around -0.7 µS. This highlights that the relaxation process in CMO/HfO x ReRAM devices leads, on average, to a decrease in the mean and an increase in the standard deviation of the Gaussian distributions regardless of the initial conductance state. Since the absolute magnitudes of the mean decrease and the standard deviation increase are independent of G target, an extended characterization of the relaxation process up to 1 week is conducted for a representative conductance state (50 µS). To achieve this, the array’s CMO/HfO x ReRAM devices are programmed using the identical-pulse closed-loop scheme to G target of 50 µS, with a 0.2% G target acceptance range. Fig. 4 e illustrates the experimental array relaxation over 1 week. The insets display the evolution of both the mean and standard deviation as a function of the logarithm of time after programming (in seconds), using a linear fit to predict the conductance distribution over a 10-year period. To assess the accuracy of analog MVM, a comprehensive set of non-idealities—both intrinsic to CMO/HfO x ReRAM devices and at the architecture level—is considered, including finite programming resolution with 0.2% G target acceptance range, conductance relaxation, limited ADC and DAC quantization, and IR-drop across array wires. Fig. 4 f shows the hardware-aware simulation results of the analog MVM using CMO/HfO x ReRAM cells, projected for up to 10 years from programming, compared to the expected floating-point (FP) result. The results are generated using a single 64×64 normally distributed random weight matrix and 100 normally distributed input vectors within the range [-1, 1] (see ”Methods” section ”HW-aware simulation of analog MVM” for details). Considering the input and output quantization of 6-bit and 8-bit respectively, the inset illustrates the time evolution of the root-mean-square error (RMSE) of the simulated analog MVM compared to the FP expected result. These results show that the CMO/HfO x ReRAM core enables accurate MVM operations, achieving an RMSE ranging from 0.03 at 1 second to 0.2 at 10 years after programming, compared to the ideal FP case. Fig. S6 in the Supplementary Information illustrates the impact of IR-drop and input/output quantization on the RMSE of an MVM performed on a 64×64 array. Over short time scales (within 1 hour), the primary accuracy bottleneck is the limited input/output quantization of 6-bit and 8-bit, respectively. Over longer periods, relaxation effects become the dominant source of non-ideality. In a larger 512×512 array, IR-drop emerges as the main accuracy bottleneck for analog MVM. Compared to the analog ReRAMs studied by Wan et al. [9], who report an experimentally determined RMSE of approximately 0.58 under conditions similar to those of this work, CMO/HfO x ReRAMs demonstrate a potential improvement in MVM accuracy by a factor of 20 and 3, 1 second and 10 years after programming, respectively. The excellent MVM accuracy results demonstrate the suitability of CMO/HfO x ReRAM devices for long-term AI inference applications, and lay the foundation for AI training acceleration, where short-term forward and backward MVMs are key steps. <details> <summary>x4.png Details</summary>  ### Visual Description ## Multi-Panel Scientific Figure: Conductance Relaxation in Memory Arrays ### Overview This image is a composite scientific figure containing six panels (a-f) that collectively analyze the relaxation (drift or decay) of conductance states in an analog memory array (likely ReRAM or a similar technology) over time. The data explores how programmed conductance values change after programming, the resulting errors, and the impact on hardware-aware matrix-vector multiplication (MVM) simulations. ### Components/Axes The figure is divided into six distinct panels, labeled **a** through **f** in the top-left corner of each subplot. * **Panel a:** Histogram titled "Array relaxation after 10min". * **X-axis:** "Programmed Conductance [µS]" (range: ~10 to 90 µS). * **Y-axis:** "Probability Density" (range: 0.00 to 1.00). * **Color Bar (Right):** Labeled "States", scale from 1 (blue) to 35 (red). * **Annotation:** A text box in the upper left states "Adjacent State Gaussian Overlap (10min): 9.6%". * **Panel b:** Scatter plot titled "Std. dev. conductance relaxation". * **X-axis:** "Programmed Conductance [µS]" (range: 10 to 90 µS). * **Y-axis:** "Standard deviation [µS]" (range: 0.0 to 1.0 µS). * **Legend (Top-Left):** Two entries: "During Programming (Acc. Range 0.2%)" (filled purple circles) and "10 min After Programming" (open light-blue circles). * **Annotation:** Two black arrows point from the "During Programming" data series upward to the "10 min After" series, with a label "Array Relaxation After 10 min". * **Panel c:** Line plot titled "G-state relaxation after 1h". * **X-axis:** "Time after programming [s]" (logarithmic scale, range: 10⁰ to ~10³ seconds). * **Y-axis:** "Programmed Conductance [µS]" (range: 10 to 90 µS). * **Data:** Multiple lines, each representing a single memory cell's conductance over time. Lines are colored on a gradient from blue (low initial conductance) to red (high initial conductance). * **Panel d:** Scatter plot titled "1h-relaxation error". * **X-axis:** "Programmed Conductance [µS]" (range: 10 to 90 µS). * **Y-axis:** "G₁ₕ - G_prog [µS]" (range: -3 to 3 µS). This represents the error after 1 hour. * **Annotation:** A horizontal dashed black line is drawn at y = -0.68 µS. A text box states "Avg. 1h-Relaxation Error = -0.68 µS". * **Data Points:** Colored circles, with color corresponding to the "States" color bar from panel **a** (blue for low states, red for high states). * **Panel e:** Composite plot titled "Extended array relaxation at 50µS". * **Main Plot (Left):** * **X-axis:** "Programmed Conductance [µS]" (range: 40 to 60 µS). * **Y-axis:** "Normalized Probability Density" (range: 0.00 to 1.00). * **Legend:** Seven entries: "Prog.", "1s", "1h", "1d", "2d", "1w", "10y". Each corresponds to a distribution curve at a different time after programming. * **Top Inset (Right):** * **X-axis:** "Log(Time[s])" (range: 0 to 20). * **Y-axis:** "Mean [µS]" (range: 45 to 50 µS). * **Data:** Points showing the mean conductance decaying over log time. A dashed green line connects the "Prog." point to the "10y" point. * **Bottom Inset (Right):** * **X-axis:** "Log(Time[s])" (range: 0 to 20). * **Y-axis:** "Std Dev. [µS]" (range: 0 to 1 µS). * **Data:** Points showing the standard deviation increasing over log time. A dashed green line connects the "Prog." point to the "10y" point. * **Panel f:** Scatter plot titled "HW-aware MVM simulations". * **X-axis:** "Expected inner product output" (range: -5.0 to 5.0). * **Y-axis:** "ReRAM inner product output" (range: -5.0 to 5.0). * **Legend (Top-Left):** Six entries: "Prog", "1s", "1h", "1d", "10y" (different colored circles), and "ideal" (solid red line). * **Annotation:** A text box states "64x64 Forward MVM 6b input, 8b output". * **Inset (Bottom-Right):** * **X-axis:** "Log(Time[s])" (range: 0 to 20). * **Y-axis:** "RMSE" (logarithmic scale, range: 10⁻² to 10⁻¹). * **Data:** Points showing the Root Mean Square Error of the MVM output increasing over log time. A dashed blue line connects the "Prog." point to the "10y" point. ### Detailed Analysis * **Panel a:** The histogram shows the distribution of conductance states across the array 10 minutes after programming. The distribution is multi-modal, with distinct peaks corresponding to the 35 programmed states. The color gradient visually maps the state number (1-35) to the conductance value. The 9.6% Gaussian overlap quantifies the probability of misidentifying adjacent states due to relaxation-induced broadening. * **Panel b:** This plot directly compares the precision of programming. The "During Programming" data (purple) shows very low standard deviation (< ~0.1 µS), indicating tight control. After 10 minutes of relaxation (light blue), the standard deviation increases significantly (to ~0.4-0.8 µS), and this increase is more pronounced for higher programmed conductance values (positive slope in the light blue data). * **Panel c:** This plot visualizes the temporal drift of individual cells. All conductance lines show a downward trend (decay) over the 1-hour period (~3600 seconds). The decay appears more severe (steeper initial slope) for cells programmed to higher conductance values (red lines) compared to lower ones (blue lines). * **Panel d:** The scatter plot shows the error (final - initial conductance) for each cell after 1 hour. The data is scattered around a negative mean (-0.68 µS), indicating a systematic downward drift. The spread (variance) of the error appears relatively consistent across the programmed conductance range, though there may be a slight increase in spread for mid-range conductances. * **Panel e:** This panel focuses on the long-term statistical evolution of a single conductance state (centered at 50 µS). The main plot shows the probability distribution broadening and shifting left (to lower conductance) over time, from "Prog." to "10y". The insets quantify this: the mean conductance decays linearly with log(time), while the standard deviation increases linearly with log(time). This is characteristic of a logarithmic relaxation process. * **Panel f:** This panel assesses the functional impact of relaxation on a computational task (64x64 matrix-vector multiplication). The main plot shows that the actual ReRAM output correlates very strongly with the expected output (data points cluster tightly around the red "ideal" line) for all time points. The inset quantifies the degradation: the RMSE of the computation increases with log(time), but remains below 0.1 even after a simulated 10 years. ### Key Observations 1. **Systematic Negative Drift:** Conductance states consistently decay over time, with an average 1-hour error of -0.68 µS (Panel d). 2. **Increased Variability:** Relaxation not only shifts the mean but also increases the standard deviation (spread) of conductance values (Panels b, e). 3. **Logarithmic Time Dependence:** Both the mean decay and the increase in standard deviation follow a linear relationship with the logarithm of time (Panel e insets). 4. **State-Dependent Effects:** Higher conductance states exhibit greater absolute standard deviation after relaxation (Panel b) and potentially faster initial decay (Panel c). 5. **Robustness in Computation:** Despite significant analog drift at the device level, the system-level performance (MVM accuracy) degrades gracefully, with RMSE increasing only moderately over a simulated decade (Panel f). ### Interpretation This figure presents a comprehensive characterization of conductance drift in an analog memory array, a critical challenge for neuromorphic computing and analog AI hardware. The data demonstrates that while individual devices undergo significant and predictable relaxation following a logarithmic law (Panels c, e), the collective behavior of a large array can be statistically modeled (Panels a, b, d). The key insight is the translation from device-level physics to system-level functionality. The "Adjacent State Gaussian Overlap" (9.6%) is a crucial metric for determining the feasibility of multi-level cell storage. Most importantly, Panel f provides a hardware-aware simulation that bridges this gap, showing that the inherent redundancy and error tolerance in neural network computations (like MVM) can mitigate the effects of analog drift. The system maintains functional accuracy even as individual components degrade, which is a promising result for the long-term reliability of analog AI accelerators. The outlier in Panel d (a point near -3 µS error) suggests occasional catastrophic failure or measurement error in single cells, which would need to be addressed through error correction or circuit design. </details> Figure 4: Conductance relaxation and MVM accuracy. a Probability density distributions of 35 conductance states approximately 10 minutes after programming. The black areas between adjacent Gaussian distributions represent the overlap of their tails. On average, an overlap of 9.6% is observed after 10 minutes. b The standard deviations of the 35 conductance states during programming (in purple) and 10 minutes after it (light blue). c Relaxation of 400 conductance states, with one device per G-state, measured 1 second and 1 hour after programming. d Relaxation error 1 hour after programming. A negative and nearly G-independent average error (dashed line) indicates that relaxation in CMO/HfO x ReRAMs tends toward a slight conductance decrease and is state-independent. e Experimental array relaxation of a representative 50 µS state, up to 1 week after programming with 0.2% G target acceptance range. Each probability density distribution is normalized to its maximum for graphical representation. The experimental data used to extract the distributions are represented as points aligned to the y=0 horizontal axis. Insets show the time dependence of the mean and standard deviation. Dashed blue lines represent the conditions during programming, once the convergence to G target is reached, while a linear fit (green dashed line) extrapolates the distribution 10 years after programming (dashed black line). f Analog MVM accuracy simulations using a 64x64 CMO/HfO x ReRAM array as a function of time after programming (indicated by different colors). The inset shows the expected RMSE compared to the ideal FP result. Experimental programming noise, conductance relaxation, limited input/output quantization and IR-drop are considered in this assessment. ### 2.3 Analog training with CMO/HfO x ReRAM core To efficiently tackle deep learning workloads, the analog AI accelerator must not only perform forward and backward passes (MVMs), but most importantly, allow for weight updates [38]. During backpropagation, the synaptic weights are modified according to the gradient of the corresponding layer. Therefore, the device conductance must be gradually modified in both positive and negative directions to represent analog weight changes. Analog CMO/HfO x ReRAM arrays not only allow for bidirectional conductance updates, but additionally enable parallel weight updating by following a stochastic open-loop pulse scheme [20, 21]. Remarkably, the parallel and open-loop update scheme significantly accelerates training compared to serial and closed-loop methods, providing efficiency gains of several orders of magnitude and advantages in system design complexity [39]. In this section, the bidirectional open-loop response of the CMO/HfO x ReRAM array, required during Tiki-Taka training, is characterized. Specifically, the analog conductance potentiation, depression and symmetry point are measured. Subsequently, the devices’ responses are statistically reproduced in the open-source ’aihwkit’ simulation platform developed by IBM [38]. Finally, this hardware-aware device model, which includes device variabilities, is used to simulate the training of representative neural networks using the AGAD learning algorithm. This novel analog training algorithm relaxes the symmetry requirements of previous Tiki-Taka versions by incorporating additional digital computations on-the-fly [23]. #### 2.3.1 Open-loop ReRAM array characterization Fig. 5 a shows the experimental conductance change of a representative CMO/HfO x ReRAM device within the array upon applying identical-voltage pulse trains with alternating polarity in batches of 400. Subsequently, a sequence of 500 pulses with alternating polarity, consisting of 1-pulse-up followed by 1-pulse-down, is applied to experimentally determine the symmetry point. The same open-loop programming scheme, with $V_{\rm set}=1.35\,\mathrm{V}$ ( $V_{\rm G}=1.4\,\mathrm{V}$ ) and $V_{\rm reset}=-1.3\,\mathrm{V}$ ( $V_{\rm G}=3.3\,\mathrm{V}$ ), each lasting 2.5 µs, is applied to all devices in the 8x4 array. The set / reset pulse width is limited by the experimental setup, although previous work has demonstrated CMO/HfO x ReRAM switching with pulses as short as $60\,\mathrm{ns}$ [25]. Due to inter-device (device-to-device) and intra-device (cycle-to-cycle) variabilities, the experimental response of each device to a given number of identical pulses exhibits some level of variability (see Fig. S7 in the Supplementary Information). Therefore, for each pulse, a Gaussian distribution of the measured conductance states among the devices is extracted. For statistical relevance, Fig. 5 b shows the experimental standard deviation of the array response to the open-loop scheme as a function of the pulse number, represented in grey. To realistically assess the accuracy of analog training with CMO/HfO x ReRAM devices, the key figures of merit of the device training characterization—such as the number of states, the symmetry point skew, and the noise-to-signal ratio (NSR)—are first extracted from experimental data, as defined below. $$ \displaystyle\mathrm{N}_{\rm states}=\frac{G_{\rm max}-G_{\rm min}}{\overline{ \Delta G_{\rm sp}}} \tag{1} $$ $$ \displaystyle\mathrm{SP}_{\rm skew}=\frac{G_{\rm max}-\overline{G_{\rm sp}}}{G _{\rm max}-G_{\rm min}} \tag{2} $$ $$ \displaystyle\mathrm{NSR}=\frac{\sigma_{\Delta G_{\rm sp}}}{\overline{\Delta G _{\rm sp}}} \tag{3} $$ $G_{\rm max}$ and $G_{\rm min}$ represent the maximum and minimum values extracted from the full conductance swings, while $\overline{G_{\rm sp}}$ , $\overline{\Delta G_{\rm sp}}$ and $\sigma_{\Delta G_{sp}}$ denote the values of the mean conductance, mean conductance update and standard deviation of the conductance update at the symmetry point during the 1-pulse-up, 1-pulse-down procedure, respectively. Fig. 5 c shows the experimental Gaussian distributions of these metrics for the 32 devices within the array. The results indicate an average of 22 states, with a range from 16 to 33. A shift in the $G_{\rm sp}$ (or SP skew) of 61% is measured, reflecting a negative trend in the device asymmetry where the down response is steeper than the up response. An average NSR of 90% among the devices is obtained, demonstrating the capability to discriminate between pulses up and down around the symmetry point. This parameter reflects the intrinsic noise on the device’s response under identical conditions, highlighting an intra-device variation [38]. Previous studies on similar CMO/HfO x ReRAM systems [24] extracted these metrics from isolated 1R devices using an optimized open-loop scheme tailored to each device. In contrast, this work demonstrates for the first time that a single open-loop identical pulse scheme enables reliable operation of the entire CMO/HfO x 1T1R array, ensuring consistent performance across the array. <details> <summary>x5.png Details</summary>  ### Visual Description ## [Technical Diagram & Charts]: ReRAM Device Characteristics and Array Metrics ### Overview This image is a composite technical figure from a research document, presenting experimental data on Resistive Random-Access Memory (ReRAM) devices. It is divided into three main panels (a, b, c) that collectively characterize the analog switching behavior of a single device, the statistical response of an 8x4 array, and key performance metrics relevant to a training algorithm called "Tiki-Taka." The figure combines a schematic diagram, time-series conductance plots, and statistical distribution histograms. ### Components/Axes **Panel a: Analog switching characteristics of a ReRAM device (open-loop)** * **Left Schematic:** An "8x4 ReRAM array" is depicted as a grid of 32 cells. Each cell is labeled with a weight notation `W(row, column)`, where rows range from 1 to 8 and columns from 1 to 4. Cells are color-coded in shades of purple, green, and teal, likely representing different conductance states or device variations. * **Top Inset (Pulse Sequence):** A timing diagram shows the applied voltage pulse sequence. * **Y-axis:** `V [V]` (Voltage in Volts). Two levels are marked: `V_set` (red, ~0.2V) and `V_reset` (blue, ~0V). * **X-axis:** Time, with pulse durations marked as `2.5µs`. * **Annotations:** Sequences of pulses are grouped with multipliers: `x400`, `x400`, `x400`, `x500`. * **Legend Box:** "Sample Device: • Potentiation: 1.35V, 2.5µs • Depression: 1.3V, 2.5µs". This defines the red and blue pulse conditions. * **Main Plot:** * **Y-axis (Left):** `Conductance [µS]` (microSiemens), on a logarithmic scale from 10 to 100. * **X-axis:** `Pulse Number`, linear scale from 0 to 2100. * **Data Series:** Two distinct series plotted as scatter points. * **Red Circles:** Correspond to "Potentiation" pulses. The trend shows conductance increasing from a low state to a high state. * **Blue Circles:** Correspond to "Depression" pulses. The trend shows conductance decreasing from a high state to a low state. * **Key Annotations:** * `G_max`: A horizontal red dashed line marking the maximum conductance level (~80-90 µS). * `G_min`: A horizontal blue dashed line marking the minimum conductance level (~15-20 µS). * `G_sp`: A horizontal yellow dashed line marking the "Symmetry Point" conductance (~40-50 µS). * `2ΔG_sp`: A vertical double-headed arrow indicating the conductance range around the symmetry point. **Panel b: Array-level open-loop statistical response** * **Main Plot:** * **Y-axis:** `Conductance [µS]`, same logarithmic scale as panel a. * **X-axis:** `Pulse Number`, same scale (0-2100). * **Data Series:** A thick, dark gray shaded band labeled "Array exp. data" in the legend (top-left). This represents the collective response of multiple devices in the array, showing the mean and spread. * **Key Annotations:** * A vertical yellow dashed line at pulse number ~1200. * `±σ`: A vertical double-headed arrow indicating the standard deviation of the conductance distribution at that pulse number. * **Inset Plot (Top Right):** * **Title:** `G after 1200 pulses [µS]` * **Y-axis:** `Probability Density`, from 0.0 to 1.0. * **X-axis:** Conductance `G [µS]`, from 60 to 120. * **Data:** A black bell curve (Gaussian distribution) with a peak around 90 µS. A shaded region under the curve is marked `±σ`. A single black dot is labeled `G_#1200`. **Panel c: Experimental array metrics for Tiki-Taka training** This panel contains three side-by-side histograms. * **Common Y-axis (All three):** `Normalized Probability Density`, from 0.0 to 1.0. * **Left Histogram:** * **X-axis:** `Number of States`, from 10 to 40. * **Data:** Purple shaded distribution with black experimental data points (`Exp.`) along the x-axis. * **Legend:** `--- Mean = 22`. * **Formula Box:** `N_states = (G_max - G_min) / ΔG_sp` * **Middle Histogram:** * **X-axis:** `Symmetry Point Skew (%)`, from 20 to 100. * **Data:** Green shaded distribution with black experimental data points. * **Legend:** `--- Mean = 61%`. * **Formula Box:** `SP_skew = (G_max - G_sp) / (G_max - G_min)` * **Right Histogram:** * **X-axis:** `Noise to Signal Ratio (%)`, from 70 to 110. * **Data:** Blue shaded distribution with black experimental data points. * **Legend:** `--- Mean = 90%`. * **Formula Box:** `NSR = σ_ΔG_sp / ΔG_sp` ### Detailed Analysis **Panel a Analysis:** The single-device characteristic shows clear, analog switching. The conductance increases (potentiates) over the first ~400 pulses, saturating near `G_max`. A subsequent depression phase (~400 pulses) reduces conductance to `G_min`. This cycle repeats. The final phase (starting at pulse 1600) shows a different behavior where conductance oscillates around the symmetry point `G_sp`, with a variation denoted by `2ΔG_sp`. The pulse sequence inset confirms that potentiation and depression are achieved with slightly different voltage amplitudes (1.35V vs. 1.3V). **Panel b Analysis:** The array-level data shows a similar potentiation-depression cycle but as a statistical ensemble. The shaded band indicates device-to-device variability. The inset probability density function confirms that after 1200 pulses, the conductance of devices in the array follows a normal (Gaussian) distribution centered at approximately 90 µS, with a standard deviation (`σ`) of roughly ±10 µS (estimated from the 60-120 µS range). **Panel c Analysis:** The three histograms quantify key metrics for the array: 1. **Number of States (`N_states`):** The distribution is centered at a mean of 22 distinct conductance states. The data points show a spread from about 15 to 30 states. 2. **Symmetry Point Skew (`SP_skew`):** The mean skew is 61%, indicating the symmetry point `G_sp` is not perfectly centered between `G_max` and `G_min`. A value of 50% would be perfectly centered; 61% suggests `G_sp` is closer to `G_max`. 3. **Noise to Signal Ratio (`NSR`):** The mean NSR is 90%, which is very high. This metric (`σ_ΔG_sp / ΔG_sp`) suggests the noise (standard deviation of conductance change around the symmetry point) is nearly as large as the signal (the conductance change itself), indicating significant variability or noise in the device's analog state. ### Key Observations 1. **Analog, Not Binary:** The ReRAM devices exhibit continuous, analog conductance modulation, not just high/low states. 2. **Cyclical Behavior:** Both single-device and array responses show repeatable potentiation and depression cycles. 3. **Device Variability:** Panel b explicitly shows the spread in conductance across the array, which is a critical challenge for analog hardware. 4. **High Noise:** The NSR mean of 90% in panel c is a standout observation, highlighting a major source of error for precise weight storage in neuromorphic computing. 5. **Asymmetry:** The `SP_skew` of 61% indicates an asymmetric switching characteristic, where the midpoint conductance is not equidistant from the extremes. ### Interpretation This figure provides a comprehensive experimental characterization of a ReRAM crossbar array intended for neuromorphic computing, specifically for a training algorithm named "Tiki-Taka." The data moves from the fundamental physics of a single device (panel a) to the collective, statistical behavior of an array (panel b), and finally to derived metrics that directly impact learning performance (panel c). The **core message** is a realistic assessment of the hardware's capabilities and limitations. While the devices successfully demonstrate analog switching—a prerequisite for synaptic weight emulation—the array exhibits substantial device-to-device variability (panel b) and high intrinsic noise (panel c, NSR=90%). The asymmetry in switching (SP_skew=61%) would also complicate symmetric weight updates during training. The "Number of States" (~22) is a practical measure of the effective bit-precision the hardware can support. For a neural network, this translates to the granularity with which synaptic weights can be represented. The combination of limited states, high noise, and asymmetry presents significant challenges for achieving high-accuracy training on this hardware, which the associated research paper likely aims to address with the "Tiki-Taka" algorithm. The figure essentially sets the stage by defining the non-ideal hardware constraints that the algorithm must overcome. </details> Figure 5: Open-loop array characterization for on-chip training. a Bidirectional accumulative response and symmetry point of a representative device in the array. The top inset shows the open-loop identical pulse scheme used for the synaptic potentiation (red) and depression (blue). A conceptual illustration of the 8x4 CMO/HfO x ReRAM array is depicted on the left. b Array statistical open-loop response to identical pulses. The grey area represents the standard deviation of the experimental Gaussian distributions, each corresponding to a specific pulse number. The inset shows a representative example of the experimental G-distribution at pulse number 1200. The raw data can be found in Figure S9 of the Supporting Information. c The experimental probability densities of N states, SP skew and NSR, respectively. The experimental data used to extract the distributions are represented as points aligned along the y=0 horizontal axis. #### 2.3.2 Tiki-Taka training simulations To perform realistic hardware-aware training simulations, the experimental device response is reproduced on software using the generalized soft bounds model implemented in the ’aihwkit’ [40], which better captures the bidirectional resistive switching behavior (see Fig. S8 in Supplementary Information) and accounts for intra- and inter-device variabilities (see cycle-to-cycle and device-to-device variations in Fig. 6 a). Additionally, Gaussian distributions are modelled based on parameters extracted from device characterization ( $G_{\rm max}$ , $G_{\rm min}$ , $\Delta G_{\rm sp}$ , NSR, SP skew) to account for device-to-device variability observed in the experimental characterization (see ”Methods” section ”Intra and inter-device variability” for details). This Gaussian fitting approach allows defining various device presets—characterized by the same model but with different parameter settings—to represent the synapses across the neural network. A realistic simulation setup is obtained by exclusively considering experimentally obtained parameters to reproduce the device trace (see ”Methods” section ”Generalized soft bounds model” for details). The device model is defined based on the observed conductance window and number of states, without assuming asymptotic behavior for an infinite number of pulses. This prevents overestimation of both the conductance window and the number of states (material states), enhancing the fidelity of the simulation. To validate analog training with CMO/HfO x ReRAM technology, a 3-layer fully connected (FC) neural network was trained on the MNIST dataset for image classification. In addition, the impact of the device’s number of states, asymmetry, and noise-to-signal ratio on accuracy and convergence time is evaluated by simulating identical networks in which each property is individually enhanced, while keeping the others fixed at the experimentally derived values. Literature has shown that these device characteristics critically influence the convergence of analog training algorithms [23]. Therefore, this method assesses the deviation of the current CMO/HfO x ReRAM device properties from the ideal analog resistive device scenario. Moreover, to show the scalability of the CMO/HfO x ReRAM technology to more computationally-intensive tasks, such as time series processing, a 2-layer long short-term memory (LSTM) network was trained on War and Peace text sequences to predict the next token. Each network is initially trained using conventional stochastic gradient descent (SGD) based backpropagation with 32-bit FP precision, serving as the baseline performance. Fig. 6 b illustrates the accuracy per epoch for the FP-baseline trained with SGD (in green) and the analog network trained using AGAD, evaluated under four different parameter settings: (1) properties extracted from the experimental array (in yellow), (2) reduced NSR to 20% (in red), (3) average of N states = 100 states (in blue), and (4) zero average device asymmetry (in orange). Using symmetrical device presets, i.e. with an average SP skew of 50%, improves accuracy by 0.7% with respect to analog training with CMO/HfO x ReRAM experimentally derived configuration (96.9%), landing an accuracy of 97.6%, a 0.7% lower than the FP-SGD baseline (98.3%). The other two configurations show less performance improvement, indicating more resilience of the AGAD-training to device’s N states and NSR. Additionally, a 2-layer LSTM network with 64 memory states each (see Fig. 6 c), is trained with the experimentally obtained configuration. The performance is measured using the exponential of the cross-entropy loss, i.e. the test perplexity metric, which quantifies the certainty of the token prediction. Results in Fig. 6 d demonstrate the capabilities of the CMO/HfO x ReRAM technology on more complex network architectures, such as LSTMs, and computationally demanding tasks, exhibiting performance comparable to the FP-equivalent, with an approximate 0.7% difference in test perplexity. <details> <summary>x6.png Details</summary>  ### Visual Description ## [Multi-Panel Technical Figure]: Device Modeling and Neural Network Training Performance ### Overview This image is a composite figure containing four panels (a, b, c, d) that collectively present data on a generalized device model, its application in training neural networks (3FC on MNIST and an LSTM), and the resulting performance metrics. The figure combines line charts and a network architecture diagram. ### Components/Axes The figure is divided into four quadrants: * **Panel a (Top-Left):** A line chart titled "Generalized soft bounds device model". * **Panel b (Top-Right):** A line chart titled "3FC MNIST training". * **Panel c (Bottom-Left):** A schematic diagram titled "LSTM network trained using CMO/HfOₓ statistical array data". * **Panel d (Bottom-Right):** A line chart titled "LSTM training". ### Detailed Analysis #### **Panel a: Generalized soft bounds device model** * **Chart Type:** Line chart with multiple data series. * **Y-Axis:** Label: "Weight". Scale ranges from -1 to 2, with major ticks at -1, 0, 1, 2. * **X-Axis:** Label: "Pulse Number". Scale ranges from 0 to 2100, with major ticks at 0, 800, 1600, 2100. * **Legend:** Located in the top-left corner. Title: "Model (C₂C and D₂D):". It defines four data series: * `Dev₁`: Dark blue diamond (♦) * `Dev₂`: Teal diamond (♦) * `Dev₃`: Green diamond (♦) * `Dev₄`: Yellow-green diamond (♦) * **Data Trends & Points:** All four series show a similar pattern of oscillation. They start near a weight of 0, rise to a plateau between ~0.5 and 1.5, drop sharply to a trough between ~-1 and 0, rise again to a second plateau, drop to a second trough, and finally rise to a third plateau. The series are vertically offset from each other, with `Dev₄` (yellow-green) generally having the highest weight values and `Dev₁` (dark blue) the lowest during the plateau phases. The data points are densely plotted, creating thick, noisy bands rather than single lines. #### **Panel b: 3FC MNIST training** * **Chart Type:** Line chart with multiple data series. * **Y-Axis:** Label: "Test Accuracy [%]". Scale ranges from 90 to 100, with major ticks every 2 units. * **X-Axis:** Label: "Epochs [a.u.]". Scale ranges from 0 to 80, with major ticks at 0, 20, 40, 60, 80. * **Legend:** Located in the bottom-right corner. It defines five data series and includes two annotations ("AGAD", "SGD") pointing to specific lines. * `CMO/HfOₓ exp. array`: Yellow diamond (♦) * `NSR down to 20%`: Red circle (●) * `Nstates up to 100`: Blue square (■) * `Symmetry (SPskew 50%)`: Orange cross (✖) * `FP-baseline`: Green plus (+) * **Data Trends & Points:** * **Trend:** All lines show increasing test accuracy with more epochs, with the rate of increase slowing over time (diminishing returns). They appear to converge towards the end of training (80 epochs). * **Key Points (Approximate at 80 Epochs):** * `FP-baseline` (Green +): Highest accuracy, ~98.5%. * `Symmetry (SPskew 50%)` (Orange ✖): ~97.8%. * `Nstates up to 100` (Blue ■): ~97.5%. * `NSR down to 20%` (Red ●): ~97.2%. * `CMO/HfOₓ exp. array` (Yellow ♦): Lowest accuracy, ~96.8%. * **Annotations:** The label "AGAD" points to the yellow diamond line (`CMO/HfOₓ exp. array`). The label "SGD" points to the green plus line (`FP-baseline`). #### **Panel c: LSTM network trained using CMO/HfOₓ statistical array data** * **Diagram Type:** Neural network architecture schematic. * **Components & Flow (Left to Right):** 1. **Input Tokens:** A vertical list of text boxes: `"The"`, `"man"`, `"walks"`, `"down"`, `"the"`. A green box at the bottom contains the target word `"street"`. 2. **To One-Hot:** A blue rectangular block. Arrows from each input token point to this block. An arrow labeled `87xN` points from this block to the next layer. 3. **LSTM 1:** A stack of teal rectangles labeled "LSTM 1". An annotation points to it: "64 hidden units". An arrow labeled `64xN` points to the next layer. 4. **LSTM 2:** A stack of teal rectangles labeled "LSTM 2". An annotation points to it: "64 hidden units". An arrow labeled `64x1` points to the next layer. 5. **FC (Fully Connected) Layer:** A vertical column of circles (neurons). An arrow labeled `64x87` points from this to the next layer. 6. **Output Layer:** A vertical column of circles. An arrow labeled `87x1` points from this to the final output. 7. **Output:** A green text box containing the predicted word `"street"`. * **Text Transcription:** All text within the diagram is in English. The input sequence is: "The", "man", "walks", "down", "the". The target/output is: "street". #### **Panel d: LSTM training** * **Chart Type:** Line chart with two data series. * **Y-Axis:** Label: "Test Perplexity". Scale ranges from 1 to 5, with major ticks at 1, 2, 3, 4, 5. * **X-Axis:** Label: "Epochs [a.u.]". Scale ranges from 0 to 100, with major ticks at 0, 20, 40, 60, 80, 100. * **Legend:** Located in the top-left corner. It defines two data series and includes annotations ("AGAD", "SGD"). * `CMO/HfOₓ exp. array`: Yellow diamond (♦) * `FP-baseline`: Green plus (+) * **Data Trends & Points:** * **Trend:** Both lines show decreasing test perplexity (lower is better) with more epochs, with the rate of decrease slowing over time. * **Key Points (Approximate):** * `FP-baseline` (Green +): Starts at ~2.4, drops rapidly, and plateaus near ~1.3 by epoch 100. * `CMO/HfOₓ exp. array` (Yellow ♦): Starts higher at ~3.4, drops steadily, and plateaus near ~2.0 by epoch 100. It remains consistently above the baseline throughout training. * **Annotations:** The label "AGAD" points to the yellow diamond line (`CMO/HfOₓ exp. array`). The label "SGD" points to the green plus line (`FP-baseline`). ### Key Observations 1. **Performance Hierarchy:** In both training tasks (3FC MNIST and LSTM), the `FP-baseline` (ideal software model) outperforms the hardware-inspired `CMO/HfOₓ exp. array` model. The experimental array shows lower accuracy and higher perplexity. 2. **Impact of Non-Idealities:** Panel b suggests that modifying specific non-idealities (like Noise-to-Signal Ratio - NSR, number of states - Nstates, or symmetry) in the model brings performance closer to the baseline, but not fully to it. 3. **Device Behavior:** Panel a shows that the generalized device model (`Dev₁` to `Dev₄`) exhibits bounded, oscillatory weight updates in response to pulses, which is characteristic of memristive or analog memory devices. The vertical offset between devices suggests device-to-device variability. 4. **Convergence:** All training curves (Panels b and d) show clear convergence, indicating the models have learned stably from the data. ### Interpretation This figure demonstrates the process and challenges of mapping ideal neural network algorithms onto non-ideal, hardware-inspired device models. Panel **a** establishes the fundamental, noisy, and bounded behavior of the underlying device. Panels **b** and **d** then show the direct consequence of using such devices (or statistical models thereof) for training: a measurable degradation in final model performance (accuracy/perplexity) compared to a perfect software baseline (`FP-baseline`). The intermediate lines in Panel **b** are crucial—they act as an ablation study, isolating which specific hardware non-idealities (noise, limited states, asymmetry) contribute most to the performance gap. The LSTM diagram in Panel **c** provides the architectural context for the results in Panel **d**. The overall narrative is one of **characterization and mitigation**: understanding device-level constraints (a) and quantifying their system-level impact (b, d) to guide the design of more robust algorithms or better devices. The persistent gap between the experimental array and the baseline highlights the ongoing challenge in achieving software-equivalent performance with analog hardware. </details> Figure 6: Device model and on-chip training simulations. a Device presets generated using the generalized soft bounds model with experimentally extracted parameters of CMO/HfO x devices, including inter- and intra-device variabilities. b Training simulations of a 3-layer fully-connected neural network on MNIST (235K parameters), using 32-bit FP precision trained on SGD (in green). Analog training simulations were performed using AGAD considering the empirical distribution of the parameters (in yellow), enhanced NSR (in red), increased N states (in blue), and symmetrical device configurations (in orange). c LSTM network architecture for text forecasting on the War and Peace dataset (79K parameters). The architecture considers a sequence length of 100 tokens and accounts for 2 layers with 64 hidden units. d Training results of the FP baseline (in green) and the analog training with AGAD on the experimental device configuration (in yellow). The training setup can be found in the Supporting Information. ## 3 Discussion An all-in-one technology platform based on analog filamentary CMO/HfO x ReRAM devices is presented. This platform addresses critical challenges in modern digital AI accelerators by overcoming the physical separation between memory and compute units. It enables the execution of forward and backward MVMs, along with weight updates and gradient computations, directly on a unified analog in-memory platform with $O(1)$ time complexity. This all-in-one approach fundamentally differs from DNN inference-only [9] and training-only [24, 41] analog accelerators. In inference-only accelerators, DNN weights are trained in software (i.e., off-chip) using traditional digital CPUs or GPUs and then programmed once onto the analog AI hardware accelerator. In training-only accelerators, the long-term retention capabilities and overall MVM accuracy for large array tiles are not assessed. In this work, a novel all-in-one analog computing platform, capable of both on-chip training and inference acceleration, is unveiled. The CMO/HfO x ReRAM devices are integrated in the BEOL of a NMOS transistor platform in a scalable 1T1R array architecture. The highly reproducible forming step demonstrates compatibility with NMOS rated for $\mathrm{3.3\,V}$ operation, while the uniform quasi-static 8W-cycling characteristics, achieved with voltage amplitudes of less than $\pm$ $\mathrm{1.5\,V}$ , exhibit a significant conductance window and a low off-state. The multi-bit capability of more than 32 states (5 bits), distinguishable after 10 minutes with less than 10% overlap error, is experimentally demonstrated using an identical-pulse closed-loop scheme. The characterization of the weight transfer reveals record-low programming noise ranging from $\mathrm{10\,nS}$ to $\mathrm{100\,nS}$ , more than one order of magnitude lower than that of other memristive technologies targeting similar conductance ranges [34, 35, 36]. Each conductance distribution exhibits a state-independent relaxation process over time, characterized by a slight shift of the mean toward lower conductance and an increase in the standard deviation. This independence of the relaxation process from the target conductance is advantageous for implementing effective compensation schemes in the future. Realistic MVM simulations on a 64x64 array tile, considering CMO/HfO x ReRAM device non-idealities such as finite weight transfer resolution, conductance relaxation, limited input/output quantization, and IR-drop across array wires, show an RMSE as low as 0.2 compared to the ideal FP-case, even 10 years after programming. This demonstrates that the CMO/HfO x ReRAM devices improve analog MVM accuracy by a factor of 20 and 3 compared to the state of the art [9], 1 second and 10 years after programming, respectively. Although this study was performed at room temperature, previous characterization of a similar CMO/HfO x ReRAM stack demonstrated the thermal stability of the analog states at high temperature (less than 4% drift after 72 hours at 85 °C) [24]. Future studies will focus on incorporating the experimental read noise of CMO/HfO x ReRAM devices, characterized between 0.2% and 2% of G target within a similar conductance range as used in this work [25], into MVM accuracy simulations. Although read noise is not included in the MVM simulations of this study, no significant additional drop in MVM accuracy is anticipated. In fact, the magnitude of read noise is much smaller than that of the relaxation process and of the effect of reduced input/output quantization, which dominate the RMSE on different timescales. Furthermore, simulation results demonstrate the suitability of CMO/HfO x ReRAM technology for large 512x512 array, with the IR-drop expected to become the primary accuracy bottleneck in this case. Finally, the electrical response of the CMO/HfO x ReRAM array to an open-loop scheme with identical pulses demonstrates the viability of this technology for on-chip training applications. A realistic device model, accounting for both inter- and intra-device variability, is derived from experimental data. Table 1 benchmarks the representative device model used in this work on the MNIST dataset against other approaches, highlighting its high fidelity in reproducing experimental device responses. Table 1: Device model benchmarking: from simplified approaches to realistic non-ideality modeling | Ti/HfO x [41] | Not-included | exp. states Measured number of analog states during open-loop device characterization. | BEOL array | TTv2 | Medium | 90.5 % | | --- | --- | --- | --- | --- | --- | --- | | Ta/TaO x [41] | Not-included | exp. states Measured number of analog states during open-loop device characterization. | BEOL array | TTv2 | Medium | 96.4 % | | TaO x /HfO x [24] | included | material states The asymptotic number of states under an infinite number of pulses. | Single ReRAMs | TTv2 | Medium | 97.4 % | | CMO x /HfO x This work. | included | exp. states Measured number of analog states during open-loop device characterization. | BEOL array | AGAD | High | 96.9 % | The impact of the device’s number of states, asymmetry and noise-to-signal ratio on training accuracy using the AGAD algorithm on MNIST is evaluated. This analysis demonstrates that, with the current device’s experimental properties, AGAD analog training achieves 96.9% accuracy, comparable to the ideal FP-baseline of 98.3%. To further improve analog training performance and bring results closer to the software equivalent, the key metric to enhance in the device is the symmetry. Finally, the on-chip analog training capabilities of the CMO/HfO x ReRAM technology are demonstrated on a more complex 2-layer LSTM network, showing comparable performance to its floating-point equivalent. In conclusion, the novel CMO/HfO x ReRAM all-in-one technology platform presented in this work lays the foundation for efficient and versatile analog chips capable of combining both training and inference capabilities, enabling autonomous, energy-efficient, and adaptable AI systems. ## 4 Methods ### 4.1 Device fabrication The CMO/HfO x ReRAM array is based on 1T1R unit cells. In this configuration, the bottom electrode of the ReRAM device is connected in series to the drain of an n-type metal–oxide–semiconductor (NMOS) selector transistor. The transistor blocks sneak paths and ensures current compliance during electro-forming and programming of the ReRAM device. The NMOS transistors, rated for $\mathrm{3.3\,V}$ operation, are fabricated using a standard $\mathrm{130\,nm}$ foundry process with copper BEOL interconnects. The ReRAM devices are integrated on metal-8 layer. To prevent the oxidation of the copper vias during the ReRAM stack deposition, the $\mathrm{70\,nm}$ thick silicon nitride (SiN x) passivation layer from the foundry is used as a protective layer. On top of that, a $\mathrm{20\,nm}$ thick titanium nitride (TiN) bottom electrode and a $\mathrm{4\,nm}$ thick hafnium oxide (HfO x) layers are deposited by Plasma-Enhanced Atomic Layer Deposition (PEALD) process at 300 °C, while maintaining vacuum conditions to avoid oxidation of the TiN layer. Subsequently, a stack of layers consisting of a $\mathrm{20\,nm}$ thick conductive metal-oxide (CMO), a $\mathrm{20\,nm}$ thick titanium nitride (TiN), and a $\mathrm{50\,nm}$ thick tungsten (W) is deposited by sputtering and patterned through a lithography step. A $\mathrm{100\,nm}$ thick silicon oxide (SiO x) layer is sputtered as passivation. The passivation layer is then patterned to expose the W top electrode and the copper via in the metal-8 layer beneath the bottom electrode. The ReRAM fabrication is completed using a titanium/gold lift-off process. In this approach, the TiN bottom electrode is connected to the metal-8 via through its vertical sidewalls using gold. The ReRAM BEOL patterning steps are performed through mask-based photolithography performed on a 6 $\times$ 6 mm 2 die issued from a Multi Project Wafer (MPW). The area of the CMO/HfO x ReRAM devices presented in this work is 12 $\times$ 12 µm 2. Previous studies on CMO/HfO x ReRAM devices have demonstrated scalability down to 200 $\times$ 200 nm 2 [24, 26, 25]. Due to their filament-type nature, the performance of the ReRAM devices presented in this work is expected to remain similar for smaller areas. ### 4.2 ReRAM forming modelling A 3D FEM of the CMO/HfO x ReRAM device, after the forming event, is used to simulate electronic transport by solving the continuity (4) and the Joule-heating (5) equations in steady state: $$ \displaystyle\nabla\cdot J_{\rm e}=\nabla\cdot(\sigma(-\nabla V)=0 \tag{4} $$ $$ \displaystyle\nabla\cdot(-k\nabla T)=J_{\rm e}\cdot E=Q_{\rm e} \tag{5} $$ where $J_{\rm e}$ is the electric current density, $\sigma$ the electrical conductivity, $V$ the electric potential, $k$ the thermal conductivity and $Q_{\rm e}$ the heat source due to Joule heating. From the fit of the experimental array forming data in the low-voltage linear regime (from 0 to $0.2\,\mathrm{V}$ ), an average filament radius of $11\,\mathrm{nm}$ is extracted. The electrical and thermal conductivities of the materials in the ReRAM stack are taken from literature [26], by considering $\sigma_{\mathrm{CMO}}=5\,\mathrm{S/cm}$ and $k_{\mathrm{CMO}}=4\,\mathrm{W/mK}$ for the CMO layer used in this work. During the subsequent negative voltage sweep, the electrical conductivity of the CMO layer was used as a fitting parameter to model the radial redistribution of defects within the layer. Using experimental array data in the low-voltage linear regime (from 0 to $\mathrm{-0.2\,V}$ ), the resulting CMO electrical conductivity is $37\,\mathrm{S/cm}$ . Fig. S1 in Supplementary Information shows the results of the simulations. ### 4.3 ReRAM forming voltage extraction The forming voltage of each 1T1R cell ( $V_{\mathrm{forming}}^{\mathrm{1T1R}}$ ) is defined as the voltage required to trigger the highest current increase ( $\max\left(\frac{dI}{dV}\right)$ ) during the quasi-static voltage sweep from 0 to $3.6\,\mathrm{V}$ (see Supplementary Information Fig. S2 a). The corresponding current is defined as the forming current ( $I_{\mathrm{forming}}^{\mathrm{1T1R}}$ ) (see Supplementary Information Fig. S2 b). Being the transistor driven by a constant $V_{\mathrm{G}}=1.2\,\mathrm{V}$ , it acts as a series resistor in the triode region before the forming event, when the ReRAM stack is highly insulating. After the forming event, when a conductive filament is created in the ReRAM device, the transistor ensures current compliance in the saturation region. The resistance of the transistor in the triode region at $V_{\mathrm{G}}=1.2\,\mathrm{V}$ is measured to be $R_{\mathrm{DS}}\approx 0.8\,\mathrm{k\Omega}$ (see Supplementary Information Fig. S2 c). Therefore, for each 1T1R cell, the actual ReRAM forming voltage is computed as $V_{\mathrm{forming}}^{\mathrm{ReRAM}}=V_{\mathrm{forming}}^{\mathrm{1T1R}}-R_{ \mathrm{DS}}^{\mathrm{triode}}\cdot I_{\mathrm{forming}}^{\mathrm{1T1R}}$ and reported in Fig. 2 c. ### 4.4 Analytical ReRAM transport modelling In the 1T1R cell, the electronic current $I_{\rm e}$ is modelled as a trap-to-trap tunneling process within the CMO layer, as described in equation (6), following the model proposed by Mott and Gurney [42]. This model accounts for electron-hopping conduction across an energy barrier $\Delta E_{\rm e}$ , which remains uniform in all directions when there is no electric field applied. However, when an electric field is introduced, it modifies the energy barrier by $\mp$ $ea_{\rm e}E$ /2 for forward (backward) jumps, leading to a reduction (increase) in the barrier height. $$ \displaystyle I_{\rm e}^{\rm Mott-Gurney}=2Aea_{\rm e}\nu_{\rm 0,e}N_{\rm e} \exp{(\frac{-\Delta E_{\rm e}}{k_{\rm B}T})}\sinh{(\frac{a_{\rm e}eE}{2k_{\rm B }T})} \tag{6} $$ In equation (6), $e$ is the elementary charge, $k_{\rm B}$ is the Boltzmann’s constant, $a_{\rm e}$ is the hopping distance, $\nu_{\rm 0,e}$ is the electron attempt frequency, $N_{\rm e}$ is the density of electronic defect states in the sub-band of the CMO layer, $\Delta E_{\rm e}$ is the zero-field hopping energy barrier, $T$ and $E$ are the local temperature and electric field, respectively, and $A=\rm\pi\it r_{\rm CF}^{\rm 2}$ , $r_{\rm CF}$ being the filament radius, is the cross-sectional area of the filament at the interface with the CMO layer. The temperature and electric field in the CMO layer, for both LRS and HRS, are simulated by solving equations (4) and (5), while accounting for the experimental I-V non-linearity (see Supplementary Fig. S4 for details). The trap-to-trap tunneling parameters ( $N_{\rm e}$ , $\Delta E_{\rm e}$ , $a_{\rm e}$ ) are extracted from the fit using the same approach as described in previous works [26, 31]. ### 4.5 Identical-pulse closed-loop scheme The procedure begins with a quasi-static voltage sweep from 0 to $-1.5\,\mathrm{V}$ to reset each cell within the array to the HRS. Subsequently, a closed-loop scheme is initiated, which iteratively repeats the following two steps until convergence to G target within an acceptance range: (1) read the conductance of the ReRAM cell, and (2) if the measured value is below (above) the target conductance, apply a set (reset) programming pulse. During this iterative process, the cell conductance may fluctuate multiple times before eventually reaching the acceptance range. Starting from the HRS, this procedure is applied to the CMO/HfO x ReRAM array to sequentially program 35 representative conductance levels, ranging from approximately 10 µS to 90 µS, using acceptance ranges of both 0.2% G target and 2% G target. Unlike the conventional incremental-pulse closed-loop technique previously used for ReRAM [9, 43], where the amplitudes of set and reset pulses are gradually increased to achieve convergence, this work employs an identical-pulse closed-loop scheme to simplify the pulse generation circuitry design, using only two fixed amplitude values for the set ( $1.35\,\mathrm{V}$ or $1.5\,\mathrm{V}$ ) and two for the reset ( $-1.3\,\mathrm{V}$ or $-1.5\,\mathrm{V}$ ) pulses. Specifically, depending on G target, three ranges are used: from approximately 10 µS to 30 µS with $V_{\rm set}=1.35\,\mathrm{V}$ and $V_{\rm reset}=-1.5\,\mathrm{V}$ ; from 30 µS to 60 µS $V_{\rm set}=1.35\,\mathrm{V}$ and $V_{\rm reset}=-1.3\,\mathrm{V}$ ; and from 60 µS to 90 µS $V_{\rm set}=1.5\,\mathrm{V}$ and $V_{\rm reset}=-1.3\,\mathrm{V}$ . Fig. S5 b in Supplementary Information shows the flowchart of the identical-pulse closed-loop technique used in this work. The set / reset pulse width is fixed at 2.5 µs due to setup limitations, even though previous work has demonstrated CMO/HfO x ReRAM switching with pulse width as short as $60\,\mathrm{ns}$ [25]. The reading pulse amplitude and width are $V_{\rm read}=0.2\,\mathrm{V}$ and 300 µs, respectively. During the set, reset, and read operations of each 1T1R cell, the transistor’s gate voltage is controlled with constant values of $V_{\rm G}$ equal to $1.4\,\mathrm{V}$ , $3.3\,\mathrm{V}$ , and $3.3\,\mathrm{V}$ , respectively. ### 4.6 HW-aware simulation of analog MVM The ’aihwkit’ [44] simulation tool was used to perform MVM assessments including non-ideal behaviors and noise, and their effect on the computation accuracy with respect to floating-point operations. The MVM simulation included the exhibited programming noise, conductance relaxation, input and output quantization, and IR-drop across array wires. The ’aihwkit’ allows to configure such noisy effects for dedicated memristive devices such as PCM by Nandakumar et al. [45] and ReRAM by Wan et al. [9]. Therefore, a unique phenomenological noise model for CMO/HfO x ReRAM devices for inference is developed to incorporate into the simulation both the characterized programming noise and conductance relaxation. Additionally, input and output are quantized with 6-bit and 8-bit resolution, respectively, and the IR-drop is considered, with 100 µS as the maximum ReRAM conductance level and a default segment wire resistance of 0.35 $\Omega$ . #### 4.6.1 Modelling the programming noise For a target conductance G target, the device’s programmed conductance is defined as the target value plus normally distributed noise with a standard deviation $\sigma_{\rm prog}$ , which is a function of G target. As depicted in Fig. 3 e, the programming noise ( $\sigma_{\rm prog}$ ) of the CMO/HfO x ReRAM devices is statistically described by a first-order polynomial equation for a given acceptance range. The polynomial coefficients for acceptance ranges of 2% and 0.2% of G target are extracted from the characterization and introduced into the simulation environment. To assess the effects of the programming noise, each weight in the normalized matrix (ranging from [-1, 1]) is mapped to its corresponding conductance value (within the range [9, 89] µS from Fig. 3 a), and is then further adjusted by the programming noise described by the extracted linear functions. Therefore, the MVM accuracy can be assessed immediately after programming ( $t=0$ ), see Fig. 4 f. #### 4.6.2 Modelling the conductance relaxation After programming, the conductance levels exhibit relaxation over time, as shown in Fig. 4. Unlike previous ReRAM drift characterizations reported by Wan et al. [9] the observed relaxation in CMO/HfO x ReRAM is approximately independent of the initial programmed conductance. Consequently, a new modelling approach in the ’aihwkit’ is needed to accurately simulate the conductance relaxation effect, which differs from the methods derived from previous literature on ReRAM [9]. The conductance relaxation mean and standard deviation are modelled independently of G target and solely as a function of time after programming. The coefficients of the first-order polynomials describing the time dependence of both the mean and standard deviation of the programmed conductance are incorporated into the simulation environment to estimate conductance variations at any given inference time. By doing so, the MVM accuracy can be estimated after a period of time up to 10 years. ### 4.7 HW-aware simulation of analog training #### 4.7.1 Generalized soft bounds model The generalized soft bounds model (SBM) selection was based on the observed characteristics of the potentiation and depression since the devices did not strictly exhibit thorough saturation at the upper and lower boundaries (see Fig. S8 in Supplementary Information). The generalized SBM incorporates a tunable scale exponent ( $\gamma$ ) that describes abrupt and gradual trends toward the maximum and minimum conductance levels. This exponent parameter also varies depending on the conductance update direction. Therefore, the analytical expression of the generalized SBM implemented in the ’aihwkit’ includes an asymmetry factor ( $\gamma_{\rm up\_down}$ ) to account for this behavior [38]. However, these two parameters do not have a direct physical equivalence, and therefore, cannot be derived from experimental traces. Hereby, $\gamma$ and $\gamma_{\rm up\_down}$ are obtained for each device through an independent linear fitting of the generalized SBM to the experimental response. In addition to the analytical parameters of the generalized SBM, devices in the ’aihwkit’ are defined by a set of parameters that can be extracted from experimental traces. More precisely, the empirical maximum and minimum conductance, minimum conductance step size and its standard deviation, and the asymmetry between up and down response are considered ( $G_{\rm max}$ , $G_{\rm min}$ , $\Delta G_{\rm sp}$ , $\sigma_{\Delta G_{\rm sp}}$ , and $up\_down$ ). More details on the $up\_down$ parameter are provided in the Supplementary Information. In this regard, each simulated device is defined by 6 parameters: four empirically obtained ( $G_{\rm max}$ , $G_{\rm min}$ , $\Delta G_{\rm sp}$ and $up\_down$ ) and two analytically modelled from SBM linear fitting ( $\gamma$ and $\gamma_{\rm up\_down}$ ). #### 4.7.2 Intra and inter-device variability By extracting the standard deviation of the minimum conductance step size ( $\sigma_{\Delta G_{\rm sp}}$ ) from the experimental traces and incorporating it into the simulation’s device model, the device response intrinsically includes noise from cycle to cycle. This provides a realistic device behavior with intra-device variability. Furthermore, the network devices shall include inter-device variabilities to perform physically accurate simulations. To achieve this, two multi-variate Gaussian distributions, G 1 and G 2, are created (see Fig. S9 in Supplementary Information). G 1 is extracted from the experimentally obtained parameters: N states (which accounts for variations across devices in the G-range and step) and SP in the normalized G-range, whereas G 2 is fitted to the analytical model parameters obtained from the fitted generalized SBM ( $\gamma$ and $\gamma_{\rm up\_down}$ ). Therefore, variables from G 1 showed statistical independence from those of G 2. New device instances are independently sampled from the two Gaussian distributions to represent synapses on the DNN layers. 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Acknowledgements The authors acknowledge the Binnig and Rohrer Nanotechnology Center (BRNC) at IBM Research Europe - Zurich. Special thanks go to Jean-Michel Portal, Eloi Muhr and Dominique Drouin for their contributions to the design of the NMOS transistors used in this work. The authors also extend their gratitude to Stephan Menzel for the fruitful discussions and to Ralph Heller for his assistance in wire-bonding the chip. This work is funded by SNSF ALMOND (grantID: 198612), by the European Union and Swiss state secretariat SERI within the H2020 MeM-Scales (grantID: 871371), MANIC (grantID: 861153), PHASTRAC (grantID: 101092096) and CHIST-ERA UNICO (20CH21-186952) projects. Author contributions Conceptualization: D. F. F. and V. B.; hardware fabrication: D. F. F. and L. B. L.; electrical characterization: D. F. F, W. C., T. S., F. H., physical simulations: D. F. F.; inference and training simulations: V. C., D. F. F.; NMOS transistor design : N. G., F. A.; result interpretation: D. F. F., V. C., W. C., V. B., M. G., A. L. P. and B. J. O., supervision: V. B. and B. J. O.; manuscript writing: D. F. F., V. C.; data curation: D. F. F., V. C. and V. B.; manuscript review and editing: all authors; funding acquisition: B. J. O. and V. B. Competing interests The authors declare no competing interests. Data availability The data that support the plots within this paper and other findings of this study are available from the corresponding authors upon reasonable request. Code availability The repositories containing the source codes used in this work for analog inference simulations and CMO/HfO x ReRAM noise model can be found at this link and this link, respectively. ## Supplementary Information <details> <summary>x7.png Details</summary>  ### Visual Description ## [Technical Diagram & Data Charts]: Memristor Device Structure and Electrical Characteristics ### Overview The image is a four-panel composite figure (labeled a, b, c, d) detailing the physical structure and electrical performance of a resistive switching memory device (memristor). Panels a and b are schematic diagrams of the device geometry and material stack. Panels c and d are data charts showing current-voltage (I-V) characteristics, with fitted models and insets illustrating the proposed physical mechanism. ### Components/Axes **Panel a: Device bird's-eye view** * **Type:** 3D wireframe schematic. * **Content:** Shows the top-down perspective of a rectangular device structure. * **Labels/Dimensions:** * Top edge: "200nm" (with a double-headed arrow indicating width). * Bottom edge: "280nm" (with a double-headed arrow indicating length). * A small circular feature is visible in the center of the top surface. **Panel b: Device y-z view** * **Type:** 2D cross-sectional schematic. * **Content:** Shows the vertical material stack of the device. * **Labels/Materials & Thicknesses (from top to bottom):** * Top and side encapsulation: "SiOₓ" * Top electrode: "W 50nm" (Tungsten, 50 nanometers thick) * Barrier/adhesion layer: "TiN 20nm" (Titanium Nitride, 20 nm) * Switching layer: "CMO 20nm" (20 nm) * Interface layer: "HfOₓ 4nm" (Hafnium Oxide, 4 nm) * Bottom electrode: "TiN 20nm" (20 nm) * A vertical line labeled "CF" (likely Conductive Filament) is drawn through the HfOₓ and CMO layers. **Panel c: Filament radius fit** * **Type:** Semi-logarithmic line chart. * **Title:** "Filament radius fit" * **Y-axis:** Label: "Current₁T₁R [A]" (Current for a 1-Transistor 1-Resistor cell, in Amperes). Scale: Logarithmic, from 10⁻⁹ to 10⁻³. * **X-axis:** Label: "Voltage₁T₁R [V]" (Voltage, in Volts). Scale: Linear, from 0.0 to 3.6. * **Legend:** A black dashed line labeled "Model". * **Data Series:** Multiple colored lines (blue to yellow gradient) representing different devices. A black dashed "Model" line follows the upper envelope of the data. * **Color Bar (Right):** Labeled "Devices". Scale: Linear, from 1 (dark blue) to 32 (yellow). Indicates the number of devices exhibiting a given I-V curve. * **Annotations:** * A circled region at low voltage (~0.1V, 10⁻⁷ A) with an arrow labeled "①" pointing to the right, indicating the SET process (transition to low resistance). * An inset schematic in the bottom-right corner showing the material stack (TiN/CMO/HfOₓ/TiN) with a conductive filament (white circles) and oxygen vacancies (Vₒ̈). Text inside: "σ̄_CMO = 5 S/cm" and "r̄_CF = 11 nm". **Panel d: CMO layer defect redistribution** * **Type:** Semi-logarithmic line chart. * **Title:** "CMO layer defect redistribution" * **Y-axis:** Label: "Current₁T₁R [A]". Scale: Logarithmic, from 10⁻⁹ to 10⁻³. * **X-axis:** Label: "Voltage₁T₁R [V]". Scale: Linear, from -1.4 to 0.0. * **Legend:** A black dashed line labeled "Model". * **Data Series:** Multiple colored lines (blue to yellow gradient) representing different devices during a RESET process (transition to high resistance). A black dashed "Model" line follows the lower envelope of the data. * **Color Bar (Right):** Identical to panel c, labeled "Devices" from 1 to 32. * **Annotations:** * A circled region at higher negative voltage (~-0.8V, 10⁻⁵ A) with an arrow labeled "②" pointing to the left, indicating the RESET process. * An inset schematic in the bottom-left corner showing the material stack. An upward yellow arrow indicates oxygen vacancy migration away from the filament. Text inside: "σ̄_CMO = 37 S/cm" and "r̄_CF = 11 nm". ### Detailed Analysis **Panel c (Filament radius fit - SET Process):** * **Trend:** The data lines show a sharp, non-linear increase in current (over 4 orders of magnitude) as voltage increases from ~0.0V to ~0.5V, characteristic of a resistive switching "SET" operation. Above ~1.0V, the current saturates near 10⁻⁴ A. * **Data Points (Approximate from Model Line):** * At 0.0V: Current ~10⁻⁸ A. * At 0.2V: Current ~10⁻⁶ A (beginning of steep rise). * At 0.5V: Current ~10⁻⁴ A (reaching high-conductance state). * At 3.6V: Current ~5x10⁻⁴ A. * **Model Parameters (Inset):** The fitted model assumes an average CMO conductivity (σ̄_CMO) of 5 S/cm and an average conductive filament radius (r̄_CF) of 11 nm. **Panel d (CMO layer defect redistribution - RESET Process):** * **Trend:** The data lines show a gradual decrease in current as the magnitude of negative voltage increases from 0.0V to ~-1.0V. This is the "RESET" process, transitioning the device back to a high-resistance state. * **Data Points (Approximate from Model Line):** * At 0.0V: Current ~10⁻⁴ A (starting from the low-resistance state). * At -0.5V: Current ~10⁻⁵ A. * At -1.0V: Current ~10⁻⁶ A. * At -1.4V: Current ~10⁻⁷ A. * **Model Parameters (Inset):** The fitted model for the RESET process assumes a higher average CMO conductivity (σ̄_CMO) of 37 S/cm, while the filament radius (r̄_CF) remains 11 nm. ### Key Observations 1. **Device Structure:** The device is a TiN/CMO/HfOₓ/TiN stack, with the CMO (20nm) and HfOₓ (4nm) layers forming the active switching medium. 2. **Switching Asymmetry:** The SET process (panel c) is abrupt and occurs at low positive voltage (<0.5V). The RESET process (panel d) is more gradual and requires higher magnitude negative voltage (>-1.0V for significant current drop). 3. **Device Variability:** The spread of colored lines in both charts indicates variability in the electrical characteristics across the 32 measured devices. The yellow lines (representing a higher count of devices) cluster around the model lines. 4. **Model Fit:** The black dashed "Model" lines provide a good fit to the envelope of the experimental data in both switching directions. 5. **Proposed Mechanism:** The insets and titles suggest the switching mechanism involves the formation/dissolution of a conductive filament (CF) with a radius of ~11 nm, coupled with the redistribution of defects (likely oxygen vacancies, Vₒ̈) within the CMO layer, altering its conductivity. ### Interpretation This figure presents a comprehensive characterization of a bilayer (CMO/HfOₓ) memristive device. The data demonstrates reliable bipolar resistive switching, where a positive voltage forms a conductive filament (SET, panel c), and a negative voltage disrupts it (RESET, panel d). The key scientific insight is the correlation between the electrical behavior and a physical model. The model successfully fits the data by accounting for two parameters: the filament radius and, crucially, the **conductivity of the CMO layer**. The significant increase in the fitted CMO conductivity (from 5 S/cm during SET to 37 S/cm during RESET) strongly suggests that the RESET process is not merely filament rupture, but involves a **redistribution of defects (oxygen vacancies) away from the filament region into the surrounding CMO matrix**, thereby increasing its overall conductivity and reducing the current through the device. This provides a more nuanced understanding of the switching mechanism beyond simple filament geometry changes. The variability shown across 32 devices highlights a common challenge in memristor technology, but the consistent fit of the model suggests the underlying physical mechanism is robust. The precise dimensions (200nm x 280nm area, specific layer thicknesses) are critical for reproducing this behavior and scaling the technology. </details> Figure S1: ReRAM forming modelling. The CMO/HfO x ReRAM device is simulated using a 3D FEM in COMSOL Multiphysics 5.2 software. a The bird’s-eye view and b the lateral y-z view of the device’s geometry and material stack are shown. Due to the temperature and electric field confinement, an effective device area of 200 $\times$ 200 nm 2 is considered for the simulation to reduce computational resource demands. c The experimental array forming data in the low-voltage linear regime (from 0 to $0.2\,\mathrm{V}$ ) are fitted to extract the average filament radius. d The increase in experimental conductance resulting from a negative voltage sweep after the forming event is modelled as an effective increase in the electrical conductivity of the CMO layer, due to a radial redistribution of defects. <details> <summary>x8.png Details</summary>  ### Visual Description ## [Chart Set]: Electrical Characterization of 1T1R and ReRAM Devices ### Overview The image is a composite of four scientific plots (labeled a, b, c, d) presenting electrical measurement data for a one-transistor-one-resistor (1T1R) memory cell and a resistive random-access memory (ReRAM) device. The plots focus on the "forming" process, which is the initial electroforming step required to activate the resistive switching element. ### Components/Axes The image is divided into four quadrants: * **Top-Left (a):** A cumulative probability plot for "1T1R forming voltage". * **Top-Right (b):** A cumulative probability plot for "1T1R forming current". * **Bottom-Left (c):** An I-V (current-voltage) curve titled "Triode resistance at V_G=1.2V". * **Bottom-Right (d):** A cumulative probability plot for "ReRAM forming voltage". **Common Elements:** * Plots a, b, and d share the same y-axis label: "Cumulative Probability [%]". * Each of these plots includes a legend in the top-left corner indicating a dashed vertical line represents the "Mean". * Each plot has a text box annotation indicating the mean value. ### Detailed Analysis #### **Subplot a: 1T1R forming voltage** * **Chart Type:** Cumulative Probability Plot. * **X-axis:** Label is `V_{forming}^{1T1R} [V]`. Scale ranges from 2 to 4 V. * **Y-axis:** "Cumulative Probability [%]". Scale is non-linear (likely a probability scale), with major ticks at 2, 10, 40, 70, 95. * **Data Series:** Blue filled circles forming an S-shaped curve. * **Legend/Annotation:** A dashed vertical black line is labeled "Mean". A text box positioned to the right of the mean line states "3.38 V". * **Trend & Data Points:** The data shows a tight distribution. The curve starts near 0% probability at ~3.1 V and reaches near 100% probability at ~3.5 V. The mean forming voltage is explicitly stated as **3.38 V**. #### **Subplot b: 1T1R forming current** * **Chart Type:** Cumulative Probability Plot. * **X-axis:** Label is `I_{forming}^{1T1R} [V]`. **Note:** The unit is incorrectly labeled as `[V]` (Volts); based on the context and the annotation, the correct unit is `[A]` (Amperes), specifically microamps (µA). Scale ranges from 100 to 500. * **Y-axis:** "Cumulative Probability [%]". Same non-linear scale as plot a. * **Data Series:** Red filled circles forming an S-shaped curve. * **Legend/Annotation:** A dashed vertical black line is labeled "Mean". A text box positioned to the right of the mean line states "258 uA". * **Trend & Data Points:** The distribution is broader than the voltage distribution in (a). The curve starts near 0% probability at ~180 µA and reaches near 100% probability at ~350 µA. The mean forming current is explicitly stated as **258 µA**. #### **Subplot c: Triode resistance at V_G=1.2V** * **Chart Type:** I-V (Current-Voltage) Curve. * **X-axis:** Label is `V_{DS} [V]` (Drain-Source Voltage). Scale is linear from 0 to 4 V. * **Y-axis:** Label is `I_{DS} [mA]` (Drain-Source Current). Scale is linear from 0.0 to 0.8 mA. * **Data Series:** A solid black line representing the measured I-V characteristic. * **Legend:** Located in the top-right quadrant of the plot. It contains two entries: 1. A solid black line labeled `V_G = 1.2 V` (Gate Voltage). 2. A thick blue line segment labeled "Triode". * **Annotations:** A text box in the lower-left quadrant points to the initial, steep linear portion of the curve (highlighted by the blue "Triode" line in the legend) and states `R_{DS}^{triode} = 0.8 kΩ`. * **Trend & Data Points:** The curve shows classic MOSFET behavior in the saturation region. At low `V_DS` (approximately 0 to 0.5 V), the current increases linearly with voltage, indicating the transistor is in the triode (linear) region. The slope of this region corresponds to a resistance of **0.8 kΩ**. For `V_DS` > 0.5 V, the current begins to saturate, increasing only gradually. #### **Subplot d: ReRAM forming voltage** * **Chart Type:** Cumulative Probability Plot. * **X-axis:** Label is `V_{forming}^{ReRAM} [V]`. Scale ranges from 2 to 4 V. * **Y-axis:** "Cumulative Probability [%]". Same non-linear scale as plots a and b. * **Data Series:** Green filled circles forming an S-shaped curve. * **Legend/Annotation:** A dashed vertical black line is labeled "Mean". A text box positioned to the right of the mean line states "3.17 V". * **Trend & Data Points:** The distribution is very tight, similar to plot (a). The curve starts near 0% probability at ~3.0 V and reaches near 100% probability at ~3.3 V. The mean forming voltage is explicitly stated as **3.17 V**. ### Key Observations 1. **Forming Voltage Consistency:** The forming voltage distributions for both the 1T1R cell (plot a, mean 3.38 V) and the standalone ReRAM element (plot d, mean 3.17 V) are very narrow, indicating a highly uniform and controllable electroforming process across multiple devices or cycles. 2. **Forming Current Variability:** The forming current distribution (plot b, mean 258 µA) is noticeably wider than the voltage distributions. This suggests that while the voltage required to initiate forming is consistent, the resulting current flow during the event has higher variability. 3. **Transistor Characterization:** Plot (c) confirms the access transistor operates correctly in the triode region at a gate bias of 1.2 V, with a well-defined on-resistance of 0.8 kΩ. This resistance is a key parameter for limiting current during ReRAM switching operations. 4. **Labeling Error:** The x-axis unit in plot (b) is incorrectly marked as `[V]` instead of `[A]` or `[µA]`. ### Interpretation This set of data characterizes the foundational electrical properties of a 1T1R memory cell, which is a common architecture for controlling ReRAM devices. The **Peircean investigative** reading reveals: * **Process Quality:** The tight cumulative probability curves for forming voltage (a, d) are strong indicators of a mature and reproducible fabrication process. Low variability in this critical parameter is essential for reliable memory array operation. * **Device Physics Insight:** The contrast between the tight voltage distribution and the broader current distribution (b) suggests that the physical mechanism of filament formation (which dictates the current path) has more inherent stochasticity than the electric field threshold required to trigger it. * **Circuit Design Implication:** The measured triode resistance (c) of 0.8 kΩ is a crucial design parameter. It determines the maximum current that can be delivered to the ReRAM element during a SET operation for a given `V_DS`, directly impacting the power consumption and switching speed of the memory cell. * **Anomaly:** The unit error on the x-axis of plot (b) is a minor but important documentation flaw that could lead to misinterpretation if not corrected. In summary, the data demonstrates a well-controlled 1T1R device with consistent forming voltages, quantifies the associated forming current and its variability, and verifies the proper operation of the selecting transistor. This information is fundamental for modeling the memory array's behavior and designing its peripheral circuitry. </details> Figure S2: Experimental CMO/HfO x ReRAM array forming data. a The forming voltage distribution of the 1T1R cells within the array, defined as the voltage required to trigger the highest current increase during the quasi-static voltage sweep from 0 to $3.6\,\mathrm{V}$ in Fig. 2 a of the manuscript. b The array forming current distribution corresponding to $V=V_{\mathrm{forming}}^{\mathrm{1T1R}}$ . c The experimental resistance of the transistor in the triode region at $V_{\mathrm{G}}=\mathrm{1.2\,V}$ , extracted from a linear fit from 0 to $0.2\,\mathrm{V}$ of the transistor output characteristic. d The forming voltage distribution of the ReRAM array, shown in Fig. 2 c of the manuscript, computed as $V_{\mathrm{forming}}^{\mathrm{ReRAM}}$ = $V_{\mathrm{forming}}^{\mathrm{1T1R}}$ - $R_{\mathrm{DS}}^{\mathrm{triode}}$ * $I_{\mathrm{forming}}^{\mathrm{1T1R}}$ . <details> <summary>x9.png Details</summary>  ### Visual Description ## Chart: RESET Characteristics of CMO-Based Resistive Switching Devices ### Overview This image is a scientific plot titled "RESET: CMO defect depletion." It displays the current-voltage (I-V) characteristics for multiple devices during a RESET operation, which transitions a resistive switching memory cell from a low-resistance state (LRS) to a high-resistance state (HRS). The plot includes a main chart and an inset schematic diagram illustrating the proposed physical mechanism. ### Components/Axes 1. **Main Chart:** * **X-axis:** `Voltage₁T₁R [V]`. The scale is linear, ranging from -1.5 V on the left to 0.0 V on the right. * **Y-axis:** `Current₁T₁R [A]`. The scale is logarithmic, ranging from 10⁻⁹ A at the bottom to 10⁻³ A at the top. * **Data Series:** Multiple colored lines, each representing the I-V curve of a single device. The lines are colored according to a gradient scale. * **Color Bar/Legend:** Located on the far right. It is labeled "Devices" and maps the line color to a device number, ranging from 1 (dark purple) to 32 (bright yellow). The gradient progresses from purple (low device number) through blue, green, to yellow (high device number). * **Annotations:** * A black arrow points from the top-right towards the center-left, indicating the general direction of the voltage sweep (from 0V to negative voltage). * A circled number "3" with a black arrow points to a specific region of the curves. * Two black circles highlight specific regions on the bundle of curves. * Dashed grey lines connect the inset diagram to the highlighted regions on the main plot. 2. **Inset Schematic Diagram (Bottom Center):** * This diagram shows a cross-section of the device stack in two states, illustrating the proposed "defect depletion" mechanism. * **Layers (from top to bottom):** * `TiN` (Titanium Nitride, top electrode) * `CMO` (Complex Metal Oxide, switching layer) * `HfOₓ` (Hafnium Oxide, another oxide layer) * `TiN` (Titanium Nitride, bottom electrode) * **Key Symbols:** * White circles: Represent oxygen vacancies (Vö), labeled as `Vö` with a dot above the 'o'. * Yellow arrows within the CMO layer: Indicate the movement or depletion of oxygen vacancies. * **Two States:** * **Left State:** Shows a dense filament of oxygen vacancies (white circles) connecting through the HfOₓ layer and extending into the CMO layer. This represents the Low-Resistance State (LRS). * **Right State:** Shows the filament in the HfOₓ layer remains, but the vacancies in the CMO layer have been depleted or dispersed away from the filament tip. This represents the High-Resistance State (HRS) after the RESET process. ### Detailed Analysis * **Data Trend:** All I-V curves show a similar trend. As the voltage sweeps from 0.0 V to -1.5 V (leftward), the current initially remains relatively high (between ~10⁻⁴ A and 10⁻³ A) and then undergoes a steep, non-linear drop (by several orders of magnitude) as the voltage becomes more negative. This drop signifies the RESET transition from LRS to HRS. * **Variability:** There is significant device-to-device variability. The voltage at which the sharp current drop occurs (the RESET voltage) varies across the 32 devices. The curves colored yellow (higher device numbers) generally appear to undergo the transition at slightly less negative voltages (closer to -1.0 V) compared to some purple/blue curves (which transition closer to -1.2 V or beyond). The final HRS current at -1.5 V also varies, spanning from below 10⁻⁸ A to nearly 10⁻⁷ A. * **Highlighted Regions:** * The upper circled region (connected to the right inset diagram) encompasses the "knee" of the curves where the current begins its steep descent. This corresponds to the onset of the RESET process. * The lower circled region (connected to the left inset diagram) is in the midst of the steep current drop, representing the active RESET transition where the conductive filament is being disrupted. ### Key Observations 1. **Universal Behavior:** All 32 devices exhibit the fundamental RESET switching characteristic—a sharp decrease in current under negative voltage bias. 2. **Stochastic Nature:** The exact RESET voltage and the slope of the transition are not identical across devices, highlighting the stochastic (random) nature of filament rupture in resistive switching memory. 3. **Correlation with Mechanism:** The inset diagram provides a physical model to explain the electrical data. The RESET process is attributed to the depletion of oxygen vacancies (defects) from the conductive filament specifically within the CMO layer, breaking the conductive path. 4. **Logarithmic Scale:** The use of a logarithmic Y-axis is essential to visualize the current change over six orders of magnitude (from mA to nA range). ### Interpretation This chart demonstrates the electrical signature and a proposed physical mechanism for the RESET operation in a TiN/CMO/HfOₓ/TiN memory device stack. * **What the data suggests:** The steep, sigmoidal drop in current under negative bias is the classic electrical indicator of a resistive switching RESET event. The variability in the curves suggests that while the underlying mechanism is consistent, the precise atomic-scale configuration of the filament and its rupture process varies from cycle to cycle and device to device. * **How elements relate:** The main plot provides the macroscopic electrical evidence (I-V curves), while the inset offers a microscopic, physical explanation. The dashed lines explicitly link the electrical behavior (the "knee" and the drop) to the proposed structural change in the device (depletion of vacancies in the CMO layer). * **Notable patterns/anomalies:** The most notable pattern is the tight bundling of curves followed by their divergence during the transition, which visually captures the interplay between a deterministic switching mechanism and its stochastic execution. There are no major outliers; all devices follow the same general path, confirming the robustness of the switching phenomenon in this material system. * **Underlying Significance:** This data is critical for understanding and optimizing resistive RAM (RRAM) devices. The RESET operation is fundamental for writing data (e.g., a "0"). The observed variability is a key challenge for large-scale memory integration, as it affects device reliability and the design of read/write circuitry. The proposed "defect depletion" model in the CMO layer offers a specific target for material engineering to improve switching uniformity and control. </details> Figure S3: The experimental array’s response to the voltage sweep from 0 to $-1.5\,\mathrm{V}$ , following the positive forming and the initial negative voltage sweep (denoted as step (1) and (2) in Fig. 2 a of the manuscript, respectively). The oxygen vacancies in the CMO layer radially spread outward, depleting the CMO defect sub-band within a half-spherical volume at the interface with the conductive filament, leading to a reset process. <details> <summary>x10.png Details</summary>  ### Visual Description ## [Chart/Diagram Type]: Composite Line Graphs (Two Panels) ### Overview The image is a composite figure containing two separate line graphs, labeled **a** and **b**, presented side-by-side. Both graphs plot a physical property of a "CMO layer" against an applied voltage. The graphs compare two distinct states: **LRS** (Low Resistance State) and **HRS** (High Resistance State). ### Components/Axes **Panel a:** * **Title:** "Average T in the CMO layer" * **Y-axis:** Label: "Temperature [K]". Scale: Linear, ranging from 293 to 500 Kelvin. Major ticks at 293, 350, 400, 450, 500. * **X-axis:** Label: "Voltage [V]". Scale: Linear, ranging from -1.0 to 0.9 Volts. Major ticks at -1.0, 0.0, 0.9. * **Legend:** Located in the top-right quadrant of the plot area. Contains two entries: * **LRS:** Represented by a solid red line. * **HRS:** Represented by a solid blue line. **Panel b:** * **Title:** "Average E in the CMO layer" * **Y-axis:** Label: "Electric Field [V/m]". Scale: **Logarithmic**, ranging from approximately 10^7 to 10^8 V/m. Major ticks at 10^7 and 10^8. * **X-axis:** Label: "Voltage [V]". Scale: Linear, identical to panel a, ranging from -1.0 to 0.9 Volts. * **Legend:** Located in the top-right quadrant of the plot area. Identical to panel a: * **LRS:** Solid red line. * **HRS:** Solid blue line. ### Detailed Analysis **Panel a (Temperature vs. Voltage):** * **Trend Verification:** * **LRS (Red Line):** Shows a steep, concave-upward decreasing trend. Temperature is highest at the most negative voltage and decreases rapidly as voltage approaches 0V. * **HRS (Blue Line):** Shows a shallow, concave-upward increasing trend. Temperature is at its minimum at 0V and increases slowly as voltage becomes positive. * **Data Points (Approximate):** * At **-1.0 V**: LRS Temperature ≈ 500 K. * At **0.0 V**: Both LRS and HRS curves meet at the minimum temperature, ≈ 293 K. * At **0.9 V**: HRS Temperature ≈ 350 K. **Panel b (Electric Field vs. Voltage):** * **Trend Verification:** * **LRS (Red Line):** Shows a steep, concave-upward decreasing trend on the log scale. Electric field is highest at the most negative voltage and decreases sharply towards 0V. * **HRS (Blue Line):** Shows a steep, concave-upward increasing trend on the log scale. Electric field is at its minimum at 0V and increases sharply as voltage becomes positive. * **Data Points (Approximate):** * At **-1.0 V**: LRS Electric Field ≈ 8 x 10^7 V/m. * At **0.0 V**: Both LRS and HRS curves meet at the minimum electric field, which appears to be just above the 10^7 V/m axis limit (estimated ≈ 1.2 x 10^7 V/m). * At **0.9 V**: HRS Electric Field ≈ 8 x 10^7 V/m. ### Key Observations 1. **Symmetry and Minimum at 0V:** Both physical properties (Temperature and Electric Field) for both resistance states (LRS and HRS) reach their minimum value at 0V bias. 2. **Inverse Relationship with Voltage Polarity:** The LRS state exhibits high values at negative voltages, while the HRS state exhibits high values at positive voltages. The curves are roughly mirror images across the 0V axis. 3. **Magnitude of Change:** The electric field (panel b) changes by nearly an order of magnitude (from ~1.2e7 to ~8e7 V/m) over the voltage range, while the temperature (panel a) changes by a factor of ~1.7 (from 293K to 500K). 4. **State-Dependent Behavior:** The LRS and HRS states are not simply different in resistance but also in their internal thermal and electrical field profiles under bias. ### Interpretation The data demonstrates the coupled electro-thermal behavior within a CMO (likely a Complex Metal Oxide) layer under electrical bias, which is characteristic of resistive switching memory devices (RRAM). * **What the data suggests:** The application of voltage generates both an electric field and Joule heating within the CMO layer. The stark difference between the LRS and HRS curves indicates that the internal distribution of current (and thus heat generation and field concentration) is fundamentally different between the two states. The LRS likely involves a more conductive filament or path, leading to high field and temperature under negative bias. The HRS likely involves a more disrupted or less conductive path, showing the opposite polarity dependence. * **How elements relate:** The two panels are directly linked. The electric field (E) drives current flow, and the resulting power dissipation (I*V or E*J, where J is current density) causes the temperature (T) rise. The minimum in both E and T at 0V is consistent with no power being dissipated at zero bias. * **Notable anomalies/trends:** The perfect alignment of the minima for both states and both properties at 0V is a key feature. The near-symmetry in magnitude between the LRS at -1V and the HRS at +0.9V in the electric field plot is also striking and suggests a designed or inherent symmetry in the switching mechanism. The logarithmic scale in panel b emphasizes that the electric field changes are exponential with voltage, a critical factor for mechanisms like ionic migration or tunneling that govern resistive switching. </details> Figure S4: The voltage-dependent evolution of a the average temperature and b electric field within a 3D half-spherical volume of the CMO layer situated atop the conductive filament in both HRS and LRS is presented. These trends serve as inputs for equation (6) of the manuscript. <details> <summary>x11.png Details</summary>  ### Visual Description ## [Chart/Diagram Type]: Composite Technical Figure (Scatter Plot and Flowchart) ### Overview The image is a two-part technical figure labeled **a** and **b**. Part **a** is a scatter plot visualizing the programming distribution of a CMO-HfOₓ ReRAM device. Part **b** is a flowchart detailing the closed-loop algorithm used to program the device to a target conductance. The overall purpose is to illustrate the precision and methodology of a conductance programming scheme for resistive memory. ### Components/Axes **Part a: CMO-HfOₓ ReRAM during programming** * **Chart Type:** Scatter plot with a color-coded third dimension. * **X-Axis:** Labeled "Target Conductance [µS]". The scale runs linearly from 10 to 90 µS, with major tick marks every 10 µS. * **Y-Axis:** Labeled "Cumulative Distribution Function". The scale runs linearly from 0.00 to 1.00, with major tick marks every 0.25. * **Data Representation:** Data points are arranged in vertical columns, each corresponding to a specific target conductance value on the x-axis. Each column contains multiple dots stacked vertically, representing the distribution of achieved conductance states for that target. * **Color Legend (States):** A vertical color bar is positioned to the right of the plot. It is labeled "States" and has a scale from 1 (bottom, blue) to 35 (top, red). The gradient transitions from dark blue (low state count) through light blue, white, orange, to dark red (high state count). * **Annotation:** A text box in the upper-left quadrant of the plot area states: "Acceptance Range: 2% G_target". **Part b: Flowchart of the closed-loop scheme** * **Chart Type:** Process flowchart. * **Title:** "Flowchart of the closed-loop scheme". * **Components & Flow:** 1. **Start (Top Rectangle):** "Calculate acceptance range (AR) based on G_target". 2. **Decision Branches (Three Paths):** Based on the value of G_target: * Left Path: `G_target ∈ [10,30]µS` → Leads to a rectangle with `V_set = 1.35V`, `V_reset = -1.5V`. * Middle Path: `G_target ∈ [30,60]µS` → Leads to a rectangle with `V_set = 1.35V`, `V_reset = -1.3V`. * Right Path: `G_target ∈ [60,90]µS` → Leads to a rectangle with `V_set = 1.5V`, `V_reset = -1.3V`. 3. **Convergence Point (Diamond):** All three paths lead to a central yellow diamond labeled "Measure G". 4. **Feedback Loops from Diamond:** * **Left Arrow (Pink Rectangle):** Condition `G < G_target - AR` → Action "Apply SET pulse (V_set)". * **Right Arrow (Blue Rectangle):** Condition `G > G_target + AR` → Action "Apply RESET pulse (V_reset)". * **Down Arrow (Green Rectangle):** Condition `G ∈ (G_target ± AR)` → Outcome "Write Succeeds". 5. **Loop Closure:** The "Apply SET pulse" and "Apply RESET pulse" actions both have arrows pointing back to the "Measure G" diamond, creating a closed-loop feedback system. ### Detailed Analysis **Part a: Data Distribution** * **Trend Verification:** For each vertical column (fixed target conductance), the data points (dots) are distributed along the y-axis (Cumulative Distribution Function). The color of the dots changes systematically from left to right across the plot. * **Spatial Grounding & Data Points:** * At low target conductance (e.g., 10 µS), the column of dots is predominantly **blue**, indicating a low number of states (approximately 1-8 according to the color bar). * As target conductance increases (moving right along the x-axis), the color of the dots in each column shifts progressively through light blue, white, and orange. * At high target conductance (e.g., 80-90 µS), the columns are predominantly **red**, indicating a high number of states (approximately 25-35). * The vertical spread (CDF range) of dots within each column appears relatively consistent across different target conductance values, suggesting a similar distribution shape, but the *number* of distinct conductance levels (states) achievable increases with the target value. **Part b: Process Logic** * The flowchart defines a precise, adaptive programming algorithm. * The **Acceptance Range (AR)** is a critical parameter, defined as 2% of the target conductance (G_target), as noted in part **a**. * The algorithm uses different programming voltages (`V_set`, `V_reset`) depending on the target conductance range, indicating that the device's response is non-linear and requires calibration. * The core is an iterative **measure-and-adjust** loop: measure conductance (G), compare it to the target window (`G_target ± AR`), and apply a corrective pulse (SET to increase conductance, RESET to decrease it) until the measured value falls within the acceptance range. ### Key Observations 1. **State Density vs. Target:** There is a clear positive correlation between the target conductance and the number of distinguishable states the device can be programmed to. Higher conductance targets allow for a finer or more numerous set of intermediate states. 2. **Adaptive Voltage Control:** The programming scheme is not one-size-fits-all. It employs three distinct voltage profiles tailored to low, medium, and high conductance regimes, likely to optimize programming speed, accuracy, or device endurance. 3. **Tight Tolerance:** The acceptance range of 2% indicates a high-precision programming requirement, necessitating the closed-loop feedback system shown in the flowchart. 4. **Visual Confirmation:** The scatter plot in **a** visually demonstrates the *result* of the process described in **b**. The tight vertical clustering of dots (within the CDF) for each target value is evidence of the algorithm's success in keeping the final conductance within a narrow band around the target. ### Interpretation This figure collectively demonstrates a sophisticated method for analog programming of a ReRAM device. The data in **a** shows that the device can be reliably placed into multiple conductance states, with the number of available states scaling with the target conductance level. This is crucial for applications like neuromorphic computing, where synaptic weights are represented by conductance values. The flowchart in **b** reveals the "how": a deterministic, feedback-controlled algorithm that compensates for device variability by iteratively measuring and adjusting. The use of different voltages for different conductance ranges suggests an underlying physical model of the device's switching behavior is being used to improve efficiency. The 2% acceptance range is a key performance metric, indicating the system's precision. **Peircean Investigation:** The sign (the image) represents an **icon** of the device's behavior (the distribution of states) and an **index** of the causal process (the algorithm) that produces that behavior. The correlation between higher target conductance and more states (red dots) is an iconic representation of increased analog capacity. The flowchart is an indexical map, pointing directly to the sequence of operations (calculate, measure, pulse) that must occur to achieve the result shown in the plot. The outlier would be any column in the plot with a color inconsistent with its neighbors (e.g., a red column at 20 µS), which would indicate a breakdown in the assumed relationship or a measurement error, but none are apparent. The system is designed for predictable, analog storage. </details> Figure S5: a The experimental cumulative distribution of conductance values for 35 representative programmed levels using 2% of G target as acceptance range. The closed-loop scheme based on identical pulses shown in Fig. 3 b of the manuscript and detailed in Methods is used. b Flowchart illustrating the identical-pulse closed-loop technique used for programming the ReRAM array into target analog conductance range. <details> <summary>x12.png Details</summary>  ### Visual Description ## Scatter Plot Comparison: I/O Quantization, IR Drop, and Scaling ### Overview The image contains two side-by-side scatter plots (labeled **a** and **b**) on a light gray background. Both plots share the same axes: a logarithmic x-axis labeled `Log(Time[s])` and a logarithmic y-axis labeled `RMSE`. The plots compare the Root Mean Square Error (RMSE) performance over time for different computational configurations, focusing on the effects of IR drop and I/O bit width for 64x64 and 512x512 systems. ### Components/Axes **Common Elements (Both Plots):** * **X-axis:** `Log(Time[s])`. Linear scale from 0 to 20. Major ticks at 0, 10, 20. * **Y-axis:** `RMSE`. Logarithmic scale from `10^-2` to `10^0` (0.01 to 1.0). Major ticks at `10^-2`, `10^-1`, `10^0`. * **Vertical Dashed Line:** A black dashed line at `Log(Time[s]) = 20`, annotated with a boxed label `10y` (likely representing 10 years). * **Horizontal Dashed Lines ("Prog."):** Three colored, dashed horizontal lines labeled `Prog.` (likely "Progress" or "Programmed target"). * **Green Dashed Line:** Positioned at approximately `RMSE = 0.03`. * **Blue Dashed Line:** Positioned at approximately `RMSE = 0.01`. * **Orange Dashed Line:** Positioned at approximately `RMSE = 0.005`. **Plot-Specific Elements:** **Plot a (Left): "64x64: I/O quantization and IR drop"** * **Legend (Top-Left):** 1. **Green 'X' marker:** `64x64: IRdrop, 6/8bit I/O (Manuscript)` 2. **Blue Square marker:** `64x64: IRdrop, 32/32bit I/O` 3. **Orange Circle marker:** `64x64: NO_IRdrop, 32/32bit I/O` * **Annotations:** Two curved arrows (one blue, one orange) point from the initial data points at `Log(Time)=0` towards the right, suggesting a progression or comparison. **Plot b (Right): "Scaling up to 512x512"** * **Legend (Top-Left):** 1. **Gray Diamond marker:** `512x512: IRdrop, 6/8bit I/O` 2. **Green 'X' marker:** `64x64: IRdrop, 6/8bit I/O (Manuscript)` (This is the same series from Plot a, included for direct comparison). ### Detailed Analysis **Plot a: 64x64 System Analysis** * **Data Series & Trends:** * **Green 'X' (6/8bit I/O with IR drop):** Shows a clear upward trend. Starts at `Log(Time)=0` with `RMSE ≈ 0.04`. Increases to `RMSE ≈ 0.1` at `Log(Time) ≈ 10`, and reaches `RMSE ≈ 0.2` at `Log(Time) = 20`. * **Blue Square (32/32bit I/O with IR drop):** Shows a very slight upward trend, nearly flat. Starts at `Log(Time)=0` with `RMSE ≈ 0.02`. Increases minimally to `RMSE ≈ 0.025` at `Log(Time) ≈ 10`, and ends at `RMSE ≈ 0.03` at `Log(Time) = 20`. * **Orange Circle (32/32bit I/O, NO IR drop):** Shows a strong upward trend. Starts at `Log(Time)=0` with the lowest `RMSE ≈ 0.015`. Increases to `RMSE ≈ 0.09` at `Log(Time) ≈ 10`, and ends at `RMSE ≈ 0.2` at `Log(Time) = 20`, converging with the green 'X' series. * **Relationship to "Prog." Lines:** The initial points for the blue and orange series are near or below their respective colored "Prog." lines (blue and orange). Over time, both the orange and green series significantly exceed their target lines, while the blue series remains close to its target. **Plot b: Scaling to 512x512 System** * **Data Series & Trends:** * **Gray Diamond (512x512, 6/8bit I/O with IR drop):** Shows a slight upward trend at a high error level. Starts at `Log(Time)=0` with `RMSE ≈ 0.5`. Increases to `RMSE ≈ 0.6` at `Log(Time) ≈ 10`, and ends at `RMSE ≈ 0.7` at `Log(Time) = 20`. * **Green 'X' (64x64, 6/8bit I/O with IR drop):** Included for scale comparison. Its values are identical to those in Plot a, appearing much lower on the RMSE scale than the 512x512 series. * **Relationship to "Prog." Lines:** The 512x512 data points are all far above the green "Prog." line (`RMSE ≈ 0.03`), indicating the larger system operates at a much higher error magnitude for the same I/O configuration. ### Key Observations 1. **Impact of IR Drop:** For the 64x64 system with 32/32bit I/O, the presence of IR drop (blue squares) dramatically stabilizes the RMSE over time compared to the no-IR-drop case (orange circles), which degrades rapidly. 2. **Impact of I/O Bit Width:** In the 64x64 system with IR drop, using lower bit-width I/O (6/8bit, green 'X') results in higher initial and final RMSE compared to using full 32/32bit I/O (blue squares). 3. **Scaling Effect:** Scaling the system from 64x64 to 512x512 (while keeping the same 6/8bit I/O with IR drop) results in an order-of-magnitude increase in RMSE (from ~0.04-0.2 to ~0.5-0.7). 4. **Convergence:** In Plot a, the `NO_IRdrop` (orange) and `IRdrop, 6/8bit` (green) series converge to similar high RMSE values at `Log(Time)=20`, despite starting from different points. 5. **Target Lines:** The "Prog." lines appear to be design targets. The 32/32bit I/O with IR drop (blue) is the only configuration that stays close to its target over the simulated time. ### Interpretation This data demonstrates critical trade-offs in hardware system design for computational tasks, likely related to analog or in-memory computing where IR drop (voltage drop) and I/O quantization are key concerns. * **The central finding is that IR drop, often seen as a non-ideality, can act as a beneficial stabilizing mechanism.** In the 64x64 system, it prevents the rapid error growth seen in the idealized "NO_IRdrop" case (orange circles). This suggests the physical constraints of IR drop may introduce a form of regularization or limit error propagation. * **There is a clear precision-performance trade-off.** Using lower-precision I/O (6/8bit) saves resources but incurs a permanent, higher RMSE penalty compared to full 32-bit I/O, both with IR drop present. * **The scaling plot (b) highlights a significant challenge.** Simply enlarging the system (to 512x512) while keeping the same low-precision I/O and experiencing IR drop leads to unacceptably high error levels (RMSE > 0.5), far exceeding the target. This indicates that scaling such systems requires more than just increasing size; it necessitates improvements in error mitigation, precision, or architecture to maintain performance. * The "10y" marker implies these are long-term reliability or degradation simulations. The upward trends in RMSE for most configurations suggest performance worsens over extended operational time, with the 32/32bit I/O with IR drop being the most robust configuration against this temporal degradation. **In summary, the charts argue that for stable, long-term operation in scaled systems, managing the interplay between physical effects (like IR drop) and architectural choices (like I/O bit width) is more crucial than simply avoiding non-idealities or increasing scale.** </details> Figure S6: The individual impact of IR-drop across array wires and input/output bit quantization on MVM accuracy. a Simulated RMSE compared to FP ideal results using 64x64 analog CMO/HfOx ReRAM array, shown as a function of the time after programming. Dashed horizontal lines represent the RMSE during programming, considering programming noise (with 0.2% G target as the acceptance range) but excluding relaxation effects. With 32-bit input/output quantization and no IR-drop (orange dots), an RMSE as low as 6 $10^{-3}$ is achieved during programming, which immediately increases (see the arrow) after relaxation (within $\mathrm{1\,s}$ ). Including the realistic IR-drop results in an overall RMSE increase (blue squares). Finally, reducing input/output quantization to 6/8 bits, respectively, leads to a further accuracy loss (green crosses), demonstrating that at short timescales (within 1 hour), the main analog MVM accuracy bottleneck is the reduced input/output quantization. After 1 hour, all cases converge, showing that the accuracy bottleneck is then dominated by the relaxation process. b By scaling up to a 512x512 array size (grey diamonds) and considering input/output quantization of 6/8 bits, IR-drop emerges as the primary bottleneck for analog MVM accuracy. <details> <summary>x13.png Details</summary>  ### Visual Description ## Line Chart Grid: Open-loop pulsed programming of the CMO-HfOx ReRAM array ### Overview The image displays a grid of 32 identical line charts arranged in an 8-row by 4-column matrix. Each chart plots the conductance of a CMO-HfOx Resistive RAM (ReRAM) device over a series of programming pulses. The overall title is "Open-loop pulsed programming of the CMO-HfOx ReRAM array." The charts demonstrate the characteristic switching behavior of these devices under a specific pulsed voltage scheme. ### Components/Axes * **Main Title:** "Open-loop pulsed programming of the CMO-HfOx ReRAM array" (centered at the top). * **Grid Structure:** 8 rows x 4 columns of individual subplots. * **X-Axis (Common to all plots):** Label: "Pulse Number". Scale: Linear, from 0 to 2100. Major tick marks at 0, 800, 1600, and 2100. * **Y-Axis (Common to all plots):** Label: "Conductance [uS]" (microSiemens). Scale: Logarithmic, spanning from 10 to 100 uS. * **Legend (Present in the top-left corner of every subplot):** * `G_min`: Blue dashed line. * `G_max`: Red dashed line. * `G_sp`: Yellow dashed line. * **Data Series:** Each plot contains three distinct data series represented by colored dots: * **Blue dots:** Correspond to the `G_min` series. * **Red dots:** Correspond to the `G_max` series. * **Yellow dots:** Correspond to the `G_sp` series. ### Detailed Analysis Each of the 32 subplots shows a nearly identical pattern of conductance evolution: 1. **Initial State (Pulse 0 ~ 800):** * **Trend:** Conductance starts at a high level. * **Values:** Both `G_max` (red) and `G_min` (blue) begin clustered near the top of the scale, approximately between 60-100 uS. The red dots (`G_max`) are consistently at the upper edge of this cluster, while the blue dots (`G_min`) are slightly lower. 2. **First Transition (Around Pulse 800):** * **Trend:** A sharp, precipitous drop in conductance occurs. * **Values:** Conductance for both series falls rapidly from the ~60-100 uS range down to the ~10-20 uS range. This represents a transition from a Low Resistance State (LRS) to a High Resistance State (HRS). 3. **Intermediate State (Pulse 800 ~ 1600):** * **Trend:** Conductance remains stable at the low level. * **Values:** Data points for both `G_max` and `G_min` are tightly clustered between approximately 10 and 20 uS. 4. **Second Transition (Around Pulse 1600):** * **Trend:** A sharp, rapid increase in conductance occurs. * **Values:** Conductance jumps from the ~10-20 uS range back up to a level between approximately 30-60 uS. This is a transition from the HRS back to an intermediate or LRS. 5. **Final State (Pulse 1600 ~ 2100):** * **Trend:** Conductance stabilizes at a new, intermediate level. * **Values:** The `G_sp` (yellow) data series appears exclusively in this region. These points form a tight, stable band between approximately 30 and 50 uS. The `G_max` (red) and `G_min` (blue) series also converge to this same band, indicating the device has settled into a specific programmed state. ### Key Observations * **High Uniformity:** All 32 devices in the array exhibit remarkably consistent switching behavior. The pulse numbers for transitions (~800 and ~1600) and the conductance levels for each state are highly reproducible across the grid. * **Bipolar Switching:** The device demonstrates clear bipolar switching: a SET process (increase in conductance) around pulse 1600 and a RESET process (decrease in conductance) around pulse 800. * **Distinct States:** Three primary conductance states are visible: a high-conductance initial state (>60 uS), a low-conductance state (~10-20 uS), and a final, stable intermediate state (~30-50 uS) labeled `G_sp`. * **Data Series Relationship:** The `G_max` (red) and `G_min` (blue) series track each other closely throughout the pulse sequence, defining the upper and lower bounds of conductance noise or variability at any given pulse. The `G_sp` (yellow) series represents the target or settled state after the final programming phase. ### Interpretation This data characterizes the fundamental analog switching properties of a CMO-HfOx ReRAM device under open-loop control. The consistent, repeatable transitions across 32 devices are crucial for memory array reliability. * **What the data demonstrates:** The charts show a deliberate, two-step programming sequence. The first ~800 pulses likely apply a RESET voltage to drive the device to a high-resistance state. The subsequent ~800 pulses (800-1600) maintain this state. The final ~500 pulses (1600-2100) apply a different (likely lower amplitude or opposite polarity) SET voltage to carefully tune the device to a specific, stable intermediate conductance level (`G_sp`). This is indicative of an analog or multi-level cell (MLC) programming scheme. * **Relationship between elements:** The `G_min` and `G_max` lines act as dynamic boundaries, showing the range of conductance fluctuation during the programming pulses. The convergence of all three data series (`G_min`, `G_max`, `G_sp`) in the final region confirms successful programming to a stable target state with minimal variability. * **Significance:** The uniformity across the array is a positive indicator for the potential use of this technology in high-density memory or neuromorphic computing applications, where consistent device-to-device behavior is essential. The ability to precisely settle at an intermediate conductance (`G_sp`) is key for implementing synaptic weights in analog hardware. The clear separation between states suggests a good on/off ratio, which is beneficial for read margins in memory applications. </details> Figure S7: The experimental response of the 8x4 CMO/HfO x ReRAM devices within the array to the open-loop programming pulse scheme (shown in Fig. 5 b of the manuscript) is shown. The set and reset pulse amplitudes are $1.35\,\mathrm{V}$ ( $V_{\mathrm{G}}=\mathrm{1.4\,V}$ ) and $-1.3\,\mathrm{V}$ ( $V_{\mathrm{G}}=\mathrm{3.3\,V}$ ), respectively, with a constant width of 2.5 µs due to setup limitations. <details> <summary>x14.png Details</summary>  ### Visual Description ## Chart: Generalized SBM vs SBM ### Overview This image is a scientific line and scatter plot comparing experimental data to two theoretical models: a "Generalized SBM" (Gen SBM) and a standard "SBM". The chart displays the evolution of a normalized quantity ("G") over a sequence of pulses. The data exhibits a clear, repeating, square-wave-like pattern with two stable states. ### Components/Axes * **Title:** "Generalized SBM vs SBM" (centered at the top). * **Y-Axis:** * **Label:** "Normalized G" (rotated vertically on the left). * **Scale:** Linear, ranging from approximately -1.3 to +1.3. * **Major Tick Marks:** -1, 0, 1. * **X-Axis:** * **Label:** "Pulse Number" (centered at the bottom). * **Scale:** Linear, ranging from 0 to 2100. * **Major Tick Marks:** 0, 800, 1600, 2100. * **Legend:** Located in the top-right corner of the plot area. * **Entry 1:** "Exp. data" represented by an open black circle symbol (○). * **Entry 2:** "Gen SBM" represented by a solid yellow line. * **Entry 3:** "SBM" represented by a solid black line. * **Data Series:** * **Experimental Data (Exp. data):** Plotted as individual circular markers. The markers are colored in two distinct groups: red and blue. The red markers cluster around the high state (~1), and the blue markers cluster around the low state (~-1). The transition regions contain a mix of both colors. * **Gen SBM Model:** A solid yellow line that follows the central trend of the experimental data points. * **SBM Model:** A solid black line that also follows the central trend, closely overlapping with the yellow "Gen SBM" line for most of the plot. ### Detailed Analysis The plot shows three complete cycles of a periodic signal, with a fourth cycle beginning. 1. **Cycle 1 (Pulse Number ~0 to ~800):** * **Trend:** The signal starts near 0, rapidly rises to a plateau near +1, holds until approximately pulse 400, then rapidly falls to a plateau near -1, holding until pulse 800. * **Data Points:** Red markers dominate the +1 plateau. Blue markers dominate the -1 plateau. The rising and falling edges show a mix of red and blue markers. * **Models:** Both the yellow (Gen SBM) and black (SBM) lines trace a sharp, square-wave-like path, rising to ~0.95 and falling to ~-1.05. They are nearly indistinguishable in this cycle. 2. **Cycle 2 (Pulse Number ~800 to ~1600):** * **Trend:** Identical pattern to Cycle 1: rapid rise to +1 plateau, then rapid fall to -1 plateau. * **Data Points:** Similar distribution of red (high) and blue (low) markers. * **Models:** Both models again closely follow the data. The yellow line (Gen SBM) appears to have a slightly smoother transition at the top of the rising edge compared to the black line (SBM). 3. **Cycle 3 (Pulse Number ~1600 to ~2100):** * **Trend:** The signal rises from -1 but does not reach the previous high of +1. Instead, it plateaus at a lower value, approximately +0.2 to +0.3. * **Data Points:** The markers in this region are a dense mix of red and blue, indicating higher variance or a different state. They cluster around the new, lower plateau level. * **Models:** Both models adjust to this new behavior. The yellow (Gen SBM) and black (SBM) lines rise and plateau at approximately +0.15, fitting the central tendency of the noisy data in this region. ### Key Observations * **Periodic Behavior:** The system demonstrates a clear, repeating, bistable behavior for the first two cycles, switching between normalized G values of ~1 and ~-1. * **Model Agreement:** Both the "Gen SBM" (yellow) and "SBM" (black) models provide an excellent fit to the experimental data's central trend throughout all cycles, including the anomalous third cycle. * **Third Cycle Anomaly:** The third cycle breaks the established pattern. The system does not return to the -1 state after pulse 1600 but instead settles at a new, positive, but sub-maximal value (~0.2). The experimental data in this region is notably noisier. * **Data Color Coding:** The experimental data points are colored red and blue. While not explicitly defined in the legend, the spatial clustering strongly suggests red corresponds to the "high" state (G ~ 1) and blue to the "low" state (G ~ -1). The mixed colors during transitions and in the third cycle indicate regions of instability or state switching. * **Visual Model Difference:** The primary visual difference between the two models is that the "Gen SBM" (yellow line) appears to have slightly rounded corners at the peaks and troughs compared to the sharper corners of the "SBM" (black line), suggesting it may be a smoothed or generalized version. ### Interpretation This chart likely presents results from a physics or engineering experiment involving a pulsed system (e.g., a spin system, an optical device, or an electronic circuit) where a measurable quantity "G" is normalized. The "SBM" probably stands for a standard theoretical model (e.g., "Spin Boson Model" or "Standard Behavioral Model"). The data demonstrates that the system can be driven between two stable states (bistability) for a number of cycles. The close fit of both models indicates they successfully capture the fundamental dynamics of this switching behavior. The critical finding is the **anomaly in the third cycle**. The system's failure to return to the -1 state and its settling at a new, noisier plateau suggests a change in experimental conditions, a degradation effect, or the onset of a new physical regime not accounted for in the initial periodic model. The fact that both models, especially the "Generalized SBM," still approximate the mean of this new state implies they may have parameters flexible enough to describe this alternate behavior, or that the anomaly is a known, modelable effect. The increased noise in the third cycle's data points further supports the idea that the system has entered a less stable or more complex dynamical phase. </details> Figure S8: The experimental open-loop pulsed response of a representative CMO/HfO x ReRAM device within the array shows that the potentiation and depression characteristics do not inherently saturate at the upper and lower boundaries. The generalized soft bounds model (yellow line) better captures this experimental trend compared to the saturated soft bounds model (black line). <details> <summary>x15.png Details</summary>  ### Visual Description ## Scatter Plot Comparison: G₁ and G₂ ### Overview The image contains two side-by-side scatter plots, labeled **a** and **b**, comparing experimental data ("Exp. array data") with data generated from a Stochastic Block Model ("Gen. SBM"). Both plots visualize the relationship between a system parameter (x-axis) and a metric named `up_down` or a variant (y-axis). The plots are designed to assess how well the generated SBM data matches the experimental array data across different conditions. ### Components/Axes **Panel a (Left):** * **Title:** `G₁` (centered above the plot area). * **X-axis:** Label is `N_states`. The scale is **logarithmic**, with major tick marks at `10¹` (10) and `10²` (100). * **Y-axis:** Label is `up_down`. The scale is linear, ranging from `-1.0` to `1.0` with major ticks at intervals of 0.5. * **Legend:** Located in the top-right corner of the plot area. * Black circle (●): `Exp. array data` * Yellow diamond (♦): `Gen. SBM` * **Data Series:** Two distinct point clouds are plotted. **Panel b (Right):** * **Title:** `G₂` (centered above the plot area). * **X-axis:** Label is the Greek letter `γ` (gamma). The scale is linear, ranging from `0.0` to `3.0` with major ticks at 0.0, 1.5, and 3.0. * **Y-axis:** Label is `γ_up_down`. The scale is linear, ranging from `-0.75` to `0.75` with major ticks at -0.75, 0.00, and 0.75. * **Legend:** Located in the top-right corner of the plot area, identical in format to panel a. * Black circle (●): `Exp. array data` * Yellow diamond (♦): `Gen. SBM` * **Data Series:** Two distinct point clouds are plotted. ### Detailed Analysis **Panel a (G₁): `up_down` vs. `N_states` (log scale)** * **Exp. array data (Black Circles):** This series forms a relatively tight, vertically oriented cluster. The points are concentrated in a narrow range of `N_states`, approximately between 20 and 50 (on the log scale). The `up_down` values for these points range roughly from -0.6 to +0.2, with the densest region centered near `up_down` = -0.2. * **Gen. SBM (Yellow Diamonds):** This series shows a much broader distribution. It spans a wider range of `N_states`, from below 10 to nearly 100. The `up_down` values also have a greater spread, from approximately -0.9 to +0.5. The cloud of yellow diamonds envelops the cluster of black circles, indicating the generated data covers a superset of the experimental parameter space but with higher variance. **Panel b (G₂): `γ_up_down` vs. `γ`** * **Exp. array data (Black Circles):** These points form a dense, roughly elliptical cluster centered around `γ` ≈ 1.5 and `γ_up_down` ≈ 0.1. The spread in `γ` is approximately from 0.8 to 2.2, and in `γ_up_down` from -0.3 to +0.5. * **Gen. SBM (Yellow Diamonds):** This series is again more dispersed than the experimental data. It covers a broader range of `γ` (from ~0.2 to ~2.8) and a significantly wider range of `γ_up_down` (from ~-0.6 to ~+0.7). The yellow diamond cloud is centered near the black circle cluster but extends much further, particularly in the vertical (`γ_up_down`) direction. ### Key Observations 1. **Consistent Pattern:** In both panels, the "Gen. SBM" data (yellow diamonds) exhibits significantly higher variance and covers a broader parameter space than the "Exp. array data" (black circles). 2. **Experimental Data Clustering:** The experimental data points are not randomly scattered; they form distinct, relatively tight clusters in both plots, suggesting the real-world system operates within a specific, constrained regime of parameters (`N_states` and `γ`). 3. **Model Envelope:** The SBM-generated data forms a "cloud" that envelops the experimental data cluster. This suggests the model is capable of generating states that include the experimentally observed ones, but also produces many other possible states not seen in the experiment. 4. **Axis Scaling:** The use of a logarithmic scale for `N_states` in panel **a** indicates that this parameter likely varies over orders of magnitude in the system being studied. ### Interpretation These plots serve as a validation or comparison tool for a Stochastic Block Model (SBM). The core finding is that while the SBM can generate data that overlaps with and encompasses the experimentally observed data (the black circles lie within the yellow cloud), the model's output is far more diverse. This discrepancy has several potential implications: * **Model Overestimation of Variance:** The SBM may be parameterized in a way that allows for too much randomness or too many possible configurations, leading to a broader distribution than what is physically realized in the experiment. * **Experimental Constraints:** The experimental setup might have inherent limitations or selection pressures that restrict the system to a narrow subset of all theoretically possible states (the tight black cluster). The model, lacking these constraints, explores the full theoretical space. * **Predictive vs. Generative Use:** The model appears better suited for *generating* a wide range of plausible system behaviors rather than *predicting* the exact, specific state of the experimental array. It captures the general region of operation but not the precise, constrained locus. In summary, the SBM successfully captures the qualitative region where the experimental system operates but quantitatively overestimates the system's variability. The experimental data suggests a more deterministic or constrained process than the purely stochastic model implies. </details> Figure S9: Multi-variate Gaussian distributions to reproduce the experimental inter-device variability. a Multi-variate gaussian G1 distribution of the experimental number of states and device asymmetry ( $up\_down$ ). b Gaussian G2 distribution of the analytical parameters $\gamma$ and $\gamma_{\rm up\_down}$ extracted from the generalized soft bounds model fitting to the experimental traces. ### Device modelling #### $up\_down$ parameter The $up\_down$ parameter is defined for the generalized soft bounds model in the simulation environment of the ‘aihwkit’ as the directional bias between the up and down update size ( $\Delta G^{+}$ and $\Delta G^{-}$ ). In addition, the minimum step in each direction d is described by the following expression [44]. $$ \displaystyle\Delta G^{d}=\Delta G_{SP}(1+d\beta+\sigma_{d-to-d}) \tag{7} $$ where d is -1 or 1 depending on the update direction. In contrast, the symmetry point is defined for each device as follows [23]: $$ \displaystyle SP=[\Delta G^{+}-\Delta G^{-}]/[\Delta G^{+}/(b_{\rm max}-\Delta G ^{+}/b_{\rm min})] \tag{8} $$ Where $\Delta G^{+}$ , $\Delta G^{-}$ define the minimum step size in the up and down direction respectively, and $b_{\rm max}$ and $b_{\rm min}$ represent the upper and lower bounds of the conductance. Therefore, considering an independent definition of each device (i.e. zero d-to-d variability) and a normalized conductance range between -1 and 1, the symmetry point device-level characteristic and the $up\_down$ analytical parameter are equivalent. #### Training setup For result replicability, the experimental parameters are incorporated into the simulation environment, where the Noise-to-Signal Ratio (NSR) is represented by ’dw_min_std’, normalized SP by ‘up_down’, normalized maximum and minimum conductances by ‘w_max’ and ‘w_min’ and min conductance step by ‘dw_min’. From this device model, analog training simulations were performed using AGAD considering a learning rate to update the weights of 1e-2, ‘fast_lr’ of 0.1 to update matrix, ‘transfer_every’ 3 iterations and batch size of 32. The FP baseline was obtained with SGD training using a learning rate of 1e-3 and batch size of 32.