2502.04524v4

# All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices **Authors**: VictoriaClerico, WooseokChoi, TommasoStecconi, FolkertHorst, LauraBégon-Lours, MatteoGaletta, AntonioLa Porta, NikhilGarg, FabienAlibart, Bert JanOffrein, ValeriaBragaglia [1] Donato Francesco Falcone 1] IBM Research - Europe, Rüschlikon, 8803, Zürich, Switzerland 2] Institut Interdisciplinaire d’Innovation Technologique (3IT), Université de Sherbrooke, Sherbrooke, QC J1K 0A5, Quebec, Canada 3] Institute of Electronics, Microelectronics and Nanotechnology (IEMN), Université de Lille, Villeneuve d’Ascq, 59650, France ## Abstract Analog in-memory computing is an emerging paradigm designed to efficiently accelerate deep neural network workloads. Recent advancements have focused on either inference or training acceleration. However, a unified analog in-memory technology platform—capable of on-chip training, weight retention, and long-term inference acceleration—has yet to be reported. This work presents an all-in-one analog AI accelerator, combining these capabilities to enable energy-efficient, continuously adaptable AI systems. The platform leverages an array of analog filamentary conductive-metal-oxide (CMO)/HfO x resistive switching memory cells (ReRAM) integrated into the back-end-of-line (BEOL). The array demonstrates reliable resistive switching with voltage amplitudes below 1.5 V, compatible with advanced technology nodes. The array’s multi-bit capability (over 32 stable states) and low programming noise (down to 10 nS) enable a nearly ideal weight transfer process, more than an order of magnitude better than other memristive technologies. Inference performance is validated through matrix-vector multiplication simulations on a 64×64 array, achieving a root-mean-square error improvement by a factor of 20 at 1 second and 3 at 10 years after programming, compared to state-of-the-art. Training accuracy closely matching the software equivalent is achieved across different datasets. The CMO/HfO x ReRAM technology lays the foundation for efficient analog systems accelerating both inference and training in deep neural networks. keywords: In-memory computing, Analog ReRAM, Deep Neural Networks, Training, Inference ## 1 Introduction Modern computing systems rely on von Neumann architectures, where instructions and data must be transferred between memory and the processing unit to perform computational tasks. This data transfer, particularly recurrent and massive in prominent artificial intelligence (AI)-related workloads, results in significant latency and energy overhead [1]. Digital AI accelerators address this challenge through computational parallelism, bringing memory closer to the processing units, and exploiting application-specific processors [2, 3]. This approach has demonstrated to bring significant improvements in throughput and efficiency for running deep neural networks (DNNs) [4], but the physical separation between memory and compute units persists. Analog in-memory computing (AIMC) [5] is a promising approach to eliminate this separation and so achieve further power and efficiency improvements in deep-learning workloads [6], by enabling some arithmetic and logic operations to be performed directly at the location where the data is stored. By mapping the weights of DNNs onto crossbar arrays of resistive devices and by leveraging Ohm’s and Kirchhoff’s physical laws, matrix-vector multiplications (MVMs)—the most recurrent operation in AI-workloads [7] —are performed in memory with $O(1)$ time complexity [5, 8, 4]. Recent demonstrations of the AIMC paradigm have primarily focused on accelerating the inference step of digitally trained DNNs [9, 10, 11, 12]. However, the increasing computing demands of modern AI models make the training phase orders of magnitude more costly in time and expenses than inference, highlighting the need for efficient hardware acceleration based on the AIMC paradigm. For instance, Gemini 1.0 Ultra required over $5\cdot 10^{25}$ floating-point operations (FLOPs), approximately 100 days, $\mathrm{24\,MW}$ of power, and an estimated cost of 30 million dollars for training [13]. Analog training acceleration imposes even more stringent requirements on resistive devices. In addition to inference (i.e., the forward pass), the back-propagation of errors, gradient computation, and weight update steps must be performed during the learning phase. However, in the digital domain updating the weights of a matrix of size NxN requires $O(N^{2})$ digital operations, leading to a significant drop in efficiency and speed. Beyond the forward pass, the AIMC approach enables acceleration of (1) backward pass through MVMs transposing the inputs and outputs, (2) gradient computation, and (3) the weight update through gradual bidirectional conductance changes upon external stimuli, all with $O(1)$ time complexity. To achieve this, the ideal analog resistive device should exhibit bidirectional, linear, and symmetric conductance updates in response to an open-loop programming pulse scheme (i.e., without the need for verification following each pulse) [4, 14]. Promising technologies include redox-based resistive switching memory (ReRAM) [15, 16], electro-chemical random access memory (ECRAM) [17], and capacitive weight elements [18]. Addressing the various non-idealities of these technologies [19] requires the co-optimization of technology and designated training algorithms. Gokmen et al. [20] proposed an efficient, fully parallel approach that leverages the coincidence of stochastic voltage pulse trains to carry out outer-product calculations and weight updates entirely within memory, in $O(1)$ time complexity. To relax the device symmetry requirements, a novel training algorithm, known as Tiki-Taka, was designed based on this parallel scheme [21]. The primary advantage of the Tiki-Taka approach lies in reduced device symmetry constraints across the entire conductance (G) range, focusing instead on a localized symmetry point where increases and decreases in G are balanced [21]. More recently, the Tiki-Taka version 2 (TTv2) algorithm was demonstrated in hardware [22] on small-scale tasks using optimized analog ReRAM technology in a 6-Transistor-1ReRAM unit cell crossbar array configuration. However, TTv2 faces some convergence issues when the reference conductance is not programmed with high precision [23]. Analog gradient accumulation with dynamic reference (AGAD) learning algorithm (i.e., TTv4) was proposed to overcome the reference conductance limitation, providing enhanced and robust performance [23]. From a technology perspective, the addition of an engineered conductive-metal-oxide (CMO) layer in a conventional HfO x -based ReRAM metal/insulator/metal (M/I/M) stack has been shown to improve switching characteristics in terms of the number of analog states, stochasticity, symmetry point, and endurance, compared to conventional M/I/M technology [24, 25, 26]. However, while CMO/HfO x ReRAM technology has proven to meet all the fundamental device criteria for on-chip training [24], array-level assessment and BEOL integration remain unexplored. Furthermore, although accelerating DNN training using AIMC is more challenging than inference, a unified technology platform capable of performing on-chip training, retaining the weights, and enabling long-term inference acceleration has yet to be reported. This work fills this gap by demonstrating an all-in-one AI accelerator based on CMO/HfO x ReRAM technology, able to perform analog acceleration of both training and long-term inference operations. Such an integrated approach paves the way for highly autonomous, energy-efficient, and continuously adaptable AI systems, opening new paths for real-time learning and inference applications. The flowchart in Fig. 1 a illustrates the all-in-one analog training and inference challenge addressed in this study. To achieve this goal, CMO/HfO x ReRAM devices, integrated into the BEOL of a $\mathrm{130\,nm}$ complementary metal-oxide-semiconductor (CMOS) technology node with copper interconnects (see ”Methods” section ”Device fabrication” for details), are arranged in an array architecture using a 1T1R unit cell. Compared to implementations that use multiple transistors to control the resistive switching, the 1T1R unit cell maximizes memory density, which is crucial for storing large AI models on a single chip. Fig. 1 b shows an image of the all-in-one analog ReRAM-based AI core used in this work, with the corresponding 8x4 array architecture and the schematic of the BEOL integrated 1T1R cells. The CMO/HfO x ReRAM array is first studied in a quasi-static regime by statistically characterizing the devices’ electro-forming step and quasi-static switching response. A physical 3D finite-element model (FEM) is developed to represent the geometry of the conductive filament and analytically describe the charge transport mechanism within these cells. Subsequently, the weight transfer accuracy and conductance relaxation are experimentally characterized on the 8x4 array. These measurements enable the demonstration of the core’s inference capabilities, validated through representative MVM accuracy simulations on a 64×64 array. After demonstrating the MVM accuracy of the CMO/HfO x ReRAM core, analog switching experiments using an open-loop identical pulse scheme demonstrated the suitability of the same core for analog on-chip training acceleration. To assess the training performance, a realistic device model was used in the simulation, accounting for measured characteristics such as non-linear and asymmetric switching behavior, as well as inter- and intra-device variabilities. The training performance was validated using AGAD on fully connected and long short-term memory (LSTM) neural networks, demonstrating scalability from small to large-scale neural networks. <details> <summary>x1.png Details</summary>  ### Visual Description ## Diagram: AIMC Training/Inference Acceleration and ReRAM-Based AI Core Architecture ### Overview The image presents two technical diagrams: 1. **AIMC Training/Inference Acceleration** (Left): A flowchart showing in-situ training and inference processes with gradient accumulation and weight updates. 2. **All-in-one Analog ReRAM-Based AI Core** (Right): A layered hardware architecture diagram illustrating a BEOL-integrated analog ReRAM array and 1T1R unit cells. --- ### Components/Axes #### AIMC Training/Inference Acceleration (Left Diagram) - **Steps**: - **In-situ Training**: - Forward pass (F) (short term) - Backward pass (B) - Gradient accumulation & Parallel Weight Update - **In-situ Inference**: - Forward pass (F) (long term) - **Components**: - Voltage sources: V₁, V₂, V₃ - Current sources: I₁, I₂ - Arrows indicate data flow direction (e.g., F → B → Gradient Update → Inference). - **Color Coding**: - Blue: Forward pass (F) - Orange: Backward pass (B) - Teal: Gradient accumulation & Weight Update #### ReRAM-Based AI Core (Right Diagram) - **Key Layers**: - **BEOL (Bottom Electrode Layer)**: - Analog ReRAM array with BL (Bit Line) and SL (Select Line) connections. - 1T1R unit cells (1 Transistor, 1 Resistor) with BL, SL, and analog ReRAM. - **Memory Stack**: - M1–M8 layers (red, blue, green, yellow) with TIN (Titanium Nitride) and CMO (Copper Manganese Oxide) materials. - **FEOL (Front Electrode Layer)**: - 130-nm n-MOSFET transistors. - **Color Coding**: - Red: M1 layer - Blue: M2–M7 layers - Green: M8 layer - Yellow: BL/SL lines --- ### Detailed Analysis #### AIMC Training/Inference Acceleration - **Training Process**: - Forward pass (F) applies input data (V₁, V₂, V₃) to the system. - Backward pass (B) propagates errors (I₁, I₂) for gradient calculation. - Gradient accumulation and parallel weight updates occur simultaneously. - **Inference Process**: - Long-term forward pass (F) uses updated weights (V₁, V₂) for predictions. #### ReRAM-Based AI Core - **1T1R Unit Cell**: - BL and SL lines control access to analog ReRAM cells. - Analog ReRAM acts as both memory and computational element. - **Material Stack**: - TIN (Titanium Nitride) and CMO (Copper Manganese Oxide) layers enable resistive switching for analog computation. - **Layering**: - M1–M8 layers form a vertical stack, with BEOL at the bottom and FEOL at the top. --- ### Key Observations 1. **AIMC Acceleration**: - Training and inference are optimized by integrating gradient updates during forward/backward passes. - Parallel weight updates reduce latency compared to traditional training. 2. **ReRAM Architecture**: - BEOL integration minimizes area overhead by embedding ReRAM directly with memory layers. - 1T1R design balances transistor control with resistive memory for energy efficiency. --- ### Interpretation - **AIMC Training**: The in-situ approach suggests a focus on real-time learning, where weights are updated dynamically during data processing. This could enable faster adaptation to new data without separate training phases. - **ReRAM Core**: The analog ReRAM array leverages resistive switching for energy-efficient computation, while the 1T1R structure ensures precise control over memory cells. The vertical layering (M1–M8) indicates a compact, high-density design suitable for edge AI applications. - **Synergy**: The AIMC training methodology likely complements the ReRAM core by enabling rapid weight updates during inference, enhancing overall system responsiveness. No numerical data or trends are present in the image. The diagrams emphasize architectural design and process flow rather than quantitative metrics. </details> Figure 1: All-in-one AIMC challenge. a Schematic representation of the key steps required to perform on-chip training and inference with analog acceleration. Each step is executed using a crossbar array of resistive devices. b CMO/HfO x ReRAM AI core used in this work, consisting of an 8×4 array of 1T1R unit cells. From a fabrication perspective, each ReRAM cell is integrated into the BEOL of a $\mathrm{130\,nm}$ NMOS transistor with copper interconnects. ## 2 Results ### 2.1 Quasi-static array characterization and modelling The quasi-static electrical characterization and analytical transport modelling of the 8x4 CMO/HfO x ReRAM array are presented here. #### 2.1.1 Filament forming Fig. 2 a shows the current-voltage characteristic of the ReRAM devices in the array, undergoing a soft-dielectric breakdown process, commonly referred to as forming [27]. During this step, a quasi-static voltage sweep up to $\mathrm{3.6\,V}$ is applied to the top electrode of each ReRAM device, while grounding the source and driving the gate of the corresponding NMOS selector with a constant $V_{\mathrm{G}}=\mathrm{1.2\,V}$ ensuring current compliance. This process leads to the formation of a highly defect-rich conductive filament in the HfO x layer. Due to the high oxygen vacancy ( $\rm V_{\rm O}^{\rm\cdot\cdot}$ in Kröger–Vink notation [28]) formation energy, ranging from $\mathrm{2.8\,eV}$ to $\mathrm{4.6\,eV}$ in HfO x depending on the stoichiometry [29, 30], defect generation occurs with statistical relevance only during the forming sweep within the HfO x layer [26]. The subsequent application of a negative voltage sweep up to $-1.4\,\mathrm{V}$ , with a constant $V_{\mathrm{G}}=\mathrm{3.3\,V}$ , induces a radial redistribution of the defects within the CMO layer, consistent with findings in literature [26]. This process leads to an increase of the ReRAM conductance and is modelled by considering a constant average radius of the conductive filament, with a local electrical conductivity increase of the CMO layer on top of the filament. Refer to the ”Methods” section ”ReRAM forming modelling” for details. To determine the experimental ReRAM forming voltage, the voltage drop across the NMOS selector must be subtracted from the voltage applied to the 1T1R cell. Fig. 2 b shows the experimental transistor output characteristic, from which the resistance in the triode region at $V_{\mathrm{G}}=\mathrm{1.2\,V}$ is measured and used to extract the distribution of $V_{\mathrm{forming}}^{\mathrm{ReRAM}}$ within the CMO/HfO x ReRAM array (reported in Fig. 2 c). Refer to the ”Methods” section ”ReRAM forming voltage extraction” for details. The highly reproducible CMO/HfO x ReRAM forming step exhibits a 100% yield with a narrow distribution ( $\sigma=\mathrm{75\,mV}$ ) around $V_{\mathrm{forming}}^{\mathrm{ReRAM}}\approx\mathrm{3.2\,V}$ , making it suitable for integration with $\mathrm{130\,nm}$ NMOS transistors rated for $\mathrm{3.3\,V}$ operation. #### 2.1.2 Resistive switching and polarity optimization The underlying physical mechanism behind the resistive switching in analog CMO/HfO x ReRAM devices has been recently unveiled [26, 31, 32]. The current transport is explained by a trap-to-trap tunneling process, and the resistive switching by a modulation of the defect density within the conductive sub-band of the CMO that behaves as electric field and temperature confinement layer. In these works, the analog CMO/HfO x ReRAM device shows a counter-eightwise (C8W) switching polarity, according to the definition proposed in literature [33]. The intrinsically gradual reset (from low to high resistance) process, marked by a temperature decrease, occurs during the positive voltage sweep on the ReRAM top electrode, while the exponential set (from high to low resistance) process, involving a rapid temperature increase, occurs on the negative side [26]. However, when arranged in a 1T1R cell configuration based on an NMOS selector, the C8W switching polarity prevents direct control of the transistor’s $V_{\mathrm{GS}}$ during the exponential set process. This results in reduced switching uniformity, which is critical for the array-level adoption of analog CMO/HfO x ReRAM devices. For this reason, in this work the analog CMO/HfO x ReRAM devices within the 1T1R cells are optimized to exhibit the desirable 8W switching polarity by extending the current switching model in literature [26]. To achieve this, following the positive forming and the initial negative voltage sweep, each device in the array is subjected to a forward and backward voltage sweep from 0 to $-1.5\,\mathrm{V}$ . During this process, oxygen vacancies in the CMO layer radially spread outward, depleting the CMO defect sub-band within a half-spherical volume at the interface with the conductive filament, leading to a reset process (Fig. S3 in Supplementary Information shows the experimental array’s response). Conversely, a voltage sweep from 0 to $1.3\,\mathrm{V}$ enables the migration of oxygen vacancies in the CMO layer in the reverse direction, resulting in a set transition, controlled by the transistor gate. For each 1T1R cell within the 8x4 array, Fig. 2 d shows 5 quasi-static I-V cycling sweeps to experimentally assess the reproducibility of the optimized 8W switching polarity. The electronic transport in both the low-resistive state (LRS) and high-resistive state (HRS) is modelled as a trap-to-trap tunneling process, described by the Mott and Gurney analytical formulation. The physical parameters characterizing the transport in both LRS and HRS ( $N_{\rm e}$ , $\Delta E_{\rm e}$ , $a_{\rm e}$ , $\sigma_{\rm CMO}$ and $r_{\rm CF}$ ) are shown in Fig. 2 d. Refer to the ”Methods” section ”Analytical ReRAM transport modelling” for details on the LRS and HRS modelling. Fig. 2 e illustrates the cumulative probability distribution of the experimental LRS and HRS within the array, demonstrating device-to-device uniformity and a resistance ratio HRS/LRS of approximately 15, with absolute switching voltages $\leq\mathrm{1.5\,V}$ . The excellent uniformity of the forming and the optimized 8W-cycling characteristics set the groundwork for AIMC-based inference and training AI-accelerators using the CMO/HfO x ReRAM technology. <details> <summary>x2.png Details</summary>  ### Visual Description ## Composite Technical Diagram: ReRAM Array Characterization ### Overview The image presents a multi-panel technical analysis of a CMOS/HfOₓ ReRAM array, combining experimental data, modeling, and device characterization. Panels a-e illustrate array forming behavior, transistor characteristics, statistical distributions, and operational states. --- ### Panel a: CMO/HfOₓ ReRAM Array Forming and Modelling #### Components/Axes - **Y-axis**: Current₁T1R [A] (log scale: 10⁻⁹ to 10⁻³) - **X-axis**: Voltage₁T1R [V] (-1.4 to 3.6) - **Legend**: Two curves with σ_CMO = 37 S/cm (green) and σ_CMO = 5 S/cm (blue), both with r_CF = 11 nm - **Inset diagrams**: Cross-sectional views of TiN/CMO/HfOₓ/TiN layers with voltage polarity indicators #### Detailed Analysis 1. **Forming Curves**: - Two distinct forming curves show current increase during voltage sweep - Higher σ_CMO (37 S/cm) exhibits steeper current rise (labeled "2" with arrow) - Lower σ_CMO (5 S/cm) shows gradual transition (labeled "1" with arrow) 2. **Voltage Thresholds**: - V_G = 1.2 V marked at upper right - Current thresholds at 10⁻⁵ A and 10⁻⁷ A indicated #### Key Observations - Higher conductivity CMO layers enable faster forming transitions - Both models predict similar final resistance states (r_CF = 11 nm) --- ### Panel b: Transistor Output Characteristic #### Components/Axes - **Y-axis**: I_DS [mA] (0 to 3) - **X-axis**: V_DS [V] (0 to 4) - **Color gradient**: V_G from 0 V (blue) to 3 V (red) - **Legend**: Color bar on right with V_G scale #### Detailed Analysis - **I-V Curves**: - All curves show saturation behavior - Higher V_G (red) corresponds to higher saturation current - Linear region slope increases with V_G - **Key Trend**: V_G modulates channel conductivity through gate voltage --- ### Panel c: Array Forming Distribution #### Components/Axes - **X-axis**: V_ReRAM_forming [V] (2.8 to 3.4) - **Y-axis**: Normalized Probability Density (0 to 1) - **Legend**: Dashed line (theoretical) vs. dots (experimental) - **Statistical markers**: Mean = 3.17 V, σ = 75 mV #### Detailed Analysis - **Distribution Shape**: - Bell-shaped curve centered at 3.17 V - Experimental data (dots) align with theoretical prediction - ±σ range spans 2.995 V to 3.345 V - **Key Insight**: Forming voltage follows Gaussian distribution with tight variance --- ### Panel d: Array Quasi-Static Cycling and Modelling #### Components/Axes - **Y-axis**: Current₁T1R [A] (10⁻⁷ to 10⁻⁴) - **X-axis**: Voltage₁T1R [V] (-1.5 to 1.3) - **Legend**: Blue (32 devices) vs. dashed yellow (model) - **Inset parameters**: - N_LRS = 5×10¹⁹ cm⁻³, ΔE_LRS = 65 meV - N_HRS = 1.2×10¹⁸ cm⁻³, ΔE_HRS = 80 meV #### Detailed Analysis - **Cycling Behavior**: - Experimental (blue) shows multi-state switching - Model (yellow) predicts idealized switching thresholds - Both show hysteresis loops with similar V_on/V_off - **Key Difference**: Experimental data exhibits broader current distribution --- ### Panel e: Array HRS-LRS Distributions #### Components/Axes - **X-axis**: Resistance [Ω] (10⁴ to 10⁵) - **Y-axis**: Cumulative Probability (%) (0 to 95) - **Legend**: Blue dots (HRS) vs. red dots (LRS) - **Statistical markers**: μ_HRS = 256 kΩ, μ_LRS = 18 kΩ; σ/μ = 0.25 for both #### Detailed Analysis - **State Separation**: - HRS (blue) dominates high-resistance tail (>10⁵ Ω) - LRS (red) occupies low-resistance region (<10⁴ Ω) - Clear bimodal distribution with minimal overlap - **Key Metric**: 95% probability threshold at 10⁵ Ω for HRS --- ### Interpretation 1. **Forming Mechanism**: Higher σ_CMO layers enable faster forming transitions, validated by steeper current rise in panel a 2. **Operational States**: Panel e confirms distinct HRS/LRS states with statistical separation, critical for binary logic applications 3. **Model Validation**: Panel d shows experimental data closely matches theoretical predictions, though real devices exhibit broader current distributions 4. **Voltage Control**: Panel b demonstrates V_G's role in modulating channel conductivity, essential for transistor operation 5. **Manufacturing Consistency**: Panel c's narrow forming voltage distribution (σ = 75 mV) suggests process control maturity The data collectively demonstrates a mature ReRAM technology with well-defined forming characteristics, stable operational states, and effective voltage control mechanisms. Experimental results closely align with theoretical models, suggesting reliable device performance across multiple fabrication batches. </details> Figure 2: ReRAM array quasi-static electrical characterization and modelling. a (1) Experimental positive forming sweeps (with $V_{\mathrm{G}}=\mathrm{1.2\,V}$ ) of the 8x4 CMO/HfO x ReRAM devices in the array. This process results in an average filament radius of $11\,\mathrm{nm}$ in the HfO x layer. (2) Negative voltage sweeps (with $V_{\mathrm{G}}=\mathrm{3.3\,V}$ ) to enable defect redistribution within the CMO layer, resulting in an increase in the conductance of the ReRAM cells. A representative sweep is shown in black. The insets illustrate a schematic representation of the defect arrangement within the stack. b Experimental NMOS transistor output characteristic, with $V_{\mathrm{G}}$ up to $\mathrm{3\,V}$ . c Experimental ReRAM forming voltage distribution measured from the CMO/HfO x ReRAM array. The experimental data used to extract the distribution are represented as green points. d Superposition of 5 I-V quasi-static 8W-cycles (in blue) for each of the 32 devices in the array, using $V_{\mathrm{set}}=\mathrm{1.3\,V}$ , $V_{\mathrm{G}}=\mathrm{1.1\,V}$ and $V_{\mathrm{reset}}=\mathrm{-1.5\,V}$ , $V_{\mathrm{G}}=\mathrm{3.3\,V}$ for set and reset processes, respectively. The analytical trap-to-trap tunneling model effectively captures the electron transport in both the LRS and HRS (yellow dashed lines). The physical parameters characterizing the transport, extracted from the model, and a schematic representation of the defect distribution, are presented for both resistive states. e Cumulative probability distributions for both LRS and HRS. For each array cell, the average resistance over 5 I-V cycles in LRS and HRS is defined at a read voltage of $\mathrm{0.2\,V}$ . ### 2.2 Analog inference with CMO/HfO x ReRAM core Here, the experimental characterization of the key metrics of the CMO/HfO x ReRAM array relevant to inference performance is presented. Specifically, the continuous conductance tuning capability is demonstrated over a range spanning approximately one order of magnitude. The trade-off between weight transfer programming noise of CMO/HfO x ReRAM devices and number of required iterations for programming convergence is analyzed across different acceptance ranges. Furthermore, conductance relaxation—defined as the change in conductance over time after programming—is characterized. Finally, the combined impact of weight transfer, conductance relaxation, limited input/output quantization of the digital-to-analog converter (DAC) and analog-to-digital converter (ADC), and IR drop on the array wires is evaluated with respect to MVM accuracy. #### 2.2.1 Weight transfer accuracy In memristor-based AIMC inference accelerators, pre-trained normalized weights are initially mapped into target conductances and subsequently programmed into hardware in an iterative process known as weight transfer. This iterative process, which stops once the programmed conductance converges to the target value within a defined acceptance range, inherently introduces an error due to the analog nature of conductance weights. This error, described by a normal distribution with the standard deviation referred to as programming noise ( $\sigma_{\rm prog}$ ), leads to a drop in MVM accuracy. To quantify this non-ideality, the non-volatile multi-level capability of the CMO/HfO x ReRAM array is characterized. Fig. 3 a shows the experimental cumulative distribution of conductance values for 35 representative levels, with all states sharply separated and without any overlap. Fig. 3 b shows a schematic representation of the closed-loop (i.e., program-verify) scheme, where identical set and reset pulse trains are employed to program each ReRAM cell to its target conductance within a desired acceptance range (see ”Methods” section ”Identical-pulse closed-loop scheme” for details). Selecting programming conditions involves a fundamental trade-off: a narrower acceptance range can improve programming precision by reducing programming noise, but it increases the number of iterations required for convergence (see Fig. 3 d). Besides the longer programming time, other non-idealities to consider when choosing the acceptance range are (1) the conductance relaxation immediately after programming, which is characterized in 2.2.2 for CMO/HfO x ReRAM devices, and (2) read noise, which has already been characterized between 0.2% and 2% of G target for CMO/HfO x ReRAM devices [25] within a similar conductance range used in this work. The trade-off between the programming noise and the number of iterations is characterized for two representative acceptance range intervals: 0.2% and 2% of G target, respectively. Fig. 3 c illustrates the experimental number of pulses needed to converge to the G target using the two representative acceptance ranges. On average, each cell requires approximately 11 and 89 set / reset pulses for acceptance ranges of 2% and 0.2% of G target, respectively. Since the acceptance range is defined as a percentage of G target, the number of iterations required for convergence is almost independent of the target conductance value. In the Supplementary Information, Fig. S5 a shows the experimental cumulative distribution of conductance values for the same 35 representative levels presented in Fig. 3 a, but using 2% G target as acceptance range. The standard deviation of the representative conductance levels is extracted and fitted as a linear function of the target conductance (dashed lines), as shown in Fig. 3 e, for both acceptance ranges. For all conductance levels, a standard deviation of less than 0.1 µS (1 µS) is achieved considering 0.2% G target (2% G target) as the acceptance range. This is more than one order of magnitude lower compared to other memristive technologies, such as phase-change memory (PCM) arrays, targeting similar conductance ranges [34, 35, 36]. These results demonstrate that CMO/HfO x ReRAM cells achieve an almost ideal weight transfer during programming, enabling the distinction of more than 32 states (5 bits). <details> <summary>x3.png Details</summary>  ### Visual Description ## Heatmap: CMO-HfOₓ ReRAM during programming ### Overview A heatmap visualizing the cumulative distribution function (CDF) of target conductance values during ReRAM programming. The color gradient represents the density of data points, with blue indicating lower values and red higher values. ### Components/Axes - **X-axis**: Target Conductance [μS] (10–90 μS) - **Y-axis**: Cumulative Distribution Function (0.00–1.00) - **Color Scale**: Blue (low density) to Red (high density) - **Legend**: "Acceptance Range: 0.2% G_target" (annotated in the top-left region) ### Detailed Analysis - The heatmap shows a gradient from blue (left) to red (right), indicating increasing conductance values. - The acceptance range (0.2% G_target) is highlighted in the upper-left quadrant, where data points cluster densely. - No explicit numerical values are provided, but the color intensity suggests higher conductance values (e.g., >70 μS) dominate the red regions. ### Key Observations - Conductance values below 30 μS are underrepresented (blue regions). - The acceptance range annotation implies a focus on conductance values near the target threshold. ### Interpretation The heatmap demonstrates the distribution of target conductance during ReRAM programming, with a concentration of data points near the 0.2% acceptance range. This suggests variability in programming outcomes, particularly at lower conductance values. --- ## Diagram: Identical-pulse closed-loop scheme ### Overview A schematic of a closed-loop programming process for ReRAM, showing voltage pulses and conductance measurements over time. ### Components/Axes - **X-axis**: Time [a.u.] (sequential steps) - **Y-axis**: Voltage States (V_set, V_read, V_reset) and Conductance (G) - **Key Elements**: - Red bars: V_set pulses - Gray bars: V_read measurements - Blue bars: V_reset pulses - Green dashed line: G_target threshold - Acceptance range: ±0.2% G_target (annotated with arrows) ### Detailed Analysis - The process alternates between V_set (programming), V_read (measurement), and V_reset (reset). - Conductance (G) is measured after each V_read, with deviations from G_target marked by the acceptance range. - The green dashed line (G_target) acts as a reference for successful programming. ### Key Observations - Conductance measurements (G) are tightly controlled within ±0.2% of G_target. - V_set pulses are consistently applied to adjust conductance toward G_target. ### Interpretation This closed-loop scheme ensures precise control of ReRAM conductance by iteratively adjusting voltage pulses and measuring deviations from the target. The acceptance range indicates tolerance for minor variations. --- ## Scatter Plot: Iterations vs G_target ### Overview A log-scale plot comparing closed-loop iterations to target conductance (G_target) for two acceptance ranges (0.2% and 2%). ### Components/Axes - **X-axis**: Target Conductance [μS] (10–90 μS) - **Y-axis**: Closed-loop Iterations (10⁰–10²) - **Legend**: - Purple: Acceptance Range 0.2% - Green: Acceptance Range 2% - Black dashed line: Average iterations per G_target ### Detailed Analysis - **0.2% Acceptance Range (Purple)**: - Iterations increase with G_target, peaking at ~100 iterations for G_target ≈ 80 μS. - Data points cluster densely between 10–50 μS. - **2% Acceptance Range (Green)**: - Fewer iterations required (1–10 iterations) across all G_target values. - Data points are sparser but show a general upward trend. ### Key Observations - Tighter acceptance ranges (0.2%) require significantly more iterations, especially at higher G_target values. - The average iterations per G_target (black dashed line) suggests a logarithmic relationship. ### Interpretation Higher precision (0.2% acceptance) demands more iterations, highlighting the trade-off between accuracy and computational effort in ReRAM programming. --- ## Heatmap: Prog. noise vs iterations ### Overview A heatmap showing the relationship between programming noise (σ_prog) and closed-loop iterations, with color gradients indicating acceptance ranges. ### Components/Axes - **X-axis**: Closed-loop Iterations (Low to High) - **Y-axis**: Programming Noise (σ_prog) [μS] - **Color Scale**: Blue (low σ_prog) to Yellow (high σ_prog) - **Annotations**: - "Trade-off: σ_prog ∈ [0.01, 0.1] μS, Iterations ≈ 90" - "σ_prog ∈ [0.1, 1] μS, Iterations ≈ 10" ### Detailed Analysis - Lower σ_prog (blue regions) correlates with higher iterations (right side of the plot). - Higher σ_prog (yellow regions) aligns with fewer iterations. - The "trade-off" annotation emphasizes the inverse relationship between noise and iterations. ### Key Observations - σ_prog values below 0.1 μS require ~90 iterations, while values above 0.1 μS drop to ~10 iterations. - The acceptance range is not explicitly labeled but inferred from color intensity. ### Interpretation Reducing programming noise improves precision but increases the number of iterations needed, reflecting a critical balance in ReRAM optimization. --- ## Scatter Plot: Prog. noise vs G_target ### Overview A log-scale plot of programming noise (σ_prog) against target conductance (G_target), with two acceptance ranges (0.2% and 2%). ### Components/Axes - **X-axis**: Target Conductance [μS] (10–90 μS) - **Y-axis**: Programming Noise (σ_prog) [μS] (10⁻²–10⁰) - **Legend**: - Purple: Acceptance Range 0.2% - Green: Acceptance Range 2% - **Equations**: - σ_prog = 10⁻³*(11.3*G + 11.2) (0.2% range) - σ_prog = 10⁻³*(1.1*G + 0.8) (2% range) ### Detailed Analysis - **0.2% Acceptance Range (Purple)**: - σ_prog increases linearly with G_target (slope ≈ 11.3*10⁻³). - Data points form a tight curve from ~0.1 μS (G=10 μS) to ~1.2 μS (G=90 μS). - **2% Acceptance Range (Green)**: - σ_prog increases more slowly (slope ≈ 1.1*10⁻³). - Data points range from ~0.08 μS (G=10 μS) to ~1.0 μS (G=90 μS). ### Key Observations - Tighter acceptance ranges (0.2%) exhibit higher σ_prog, especially at higher G_target values. - The 2% range shows a flatter trend, indicating lower noise tolerance. ### Interpretation Programming noise scales with target conductance, with stricter acceptance ranges amplifying noise effects. This underscores the challenge of maintaining precision in high-conductance ReRAM devices. </details> Figure 3: Weight transfer characterization. a Cumulative distributions of 35 conductance states obtained using an identical-pulse closed-loop scheme with a 0.2% G target acceptance range. For each distribution, the entire CMO/HfO x ReRAM array was programmed to the corresponding G target, and the conductance values measured during the final closed-loop iteration (during programming) is reported. Each dot represents a 1T1R cell. b An example sequence of the identical-pulse closed-loop programming scheme utilized in this work. c Experimental number of closed-loop iterations as a function of G target for the two representative acceptance ranges. Each semitransparent point represents a 1T1R cell, the opaque points represent the average number of iterations per G target, and the horizontal dashed line indicates the overall average of the opaque points. d Graphical representation of the trade-off between programming noise and the number of iterations required for convergence, as a function of the acceptance range. e Experimental programming noise as a function of G target for the two representative acceptance ranges. Each point represents the standard deviation of the normal distribution measured across the entire array. The dashed lines in black indicate the corresponding linear fits. #### 2.2.2 Conductance relaxation and matrix-vector multiplication accuracy In addition to the excellent weight transfer accuracy during programming as presented in the previous section, the characterization of temporal conductance relaxation is critical to estimate the MVM accuracy over time. In analog ReRAM devices, a significant conductance relaxation has been observed immediately after programming (within 1 second) [9]. Following this initial abrupt conductance change, the relaxation process slows considerably [37, 9]. The physical cause of retention degradation is attributed to the Brownian motion of defects in the resistive switching layer [37]. In this section, the conductance relaxation of the CMO/HfO x ReRAM array after programming is characterized. Fig. 4 a shows the relaxation of the distributions previously reported in Fig. 3 a, approximately 10 minutes after programming. The 35 levels remain distinguishable 10 minutes after programming, with an average overlap of 9.6% between adjacent states gaussians, while the average standard deviation of the distributions increases to 0.6 µS, showing almost independence from the G target (see Fig. 4 b). The stability of the CMO/HfO x ReRAM conductance states is further assessed on a longer time-scale, up to 1 hour. To achieve so, a linearly spaced G target vector within the experimental conductance range of 10 µS to 90 µS is defined, with a fine step of 0.2 µS (400 points). Each G target value is programmed into a single ReRAM device within the array. Due to the size mismatch between the array (32 devices) and the G target vector (size 400), multiple measurement batches are needed. Fig. 4 c shows the experimental relaxation of the 400 programmed states within the entire conductance window, 1 second and 1 hour after programming, executed with the closed-loop scheme (see ”Methods” section ”Identical-pulse closed-loop scheme” for details) and with a 0.2% G target acceptance range. The exhibited conductance error induced by the relaxation process after 1 hour, computed as $G_{\mathrm{1h}}-G_{\mathrm{prog.}}$ , is plotted as a function of the programmed conductances in Fig. 4 d. After 1 hour, although both positive and negative relaxation errors are recorded, an average decrease in conductance is observed across all programmed states, with a relaxation error averaging around -0.7 µS. This highlights that the relaxation process in CMO/HfO x ReRAM devices leads, on average, to a decrease in the mean and an increase in the standard deviation of the Gaussian distributions regardless of the initial conductance state. Since the absolute magnitudes of the mean decrease and the standard deviation increase are independent of G target, an extended characterization of the relaxation process up to 1 week is conducted for a representative conductance state (50 µS). To achieve this, the array’s CMO/HfO x ReRAM devices are programmed using the identical-pulse closed-loop scheme to G target of 50 µS, with a 0.2% G target acceptance range. Fig. 4 e illustrates the experimental array relaxation over 1 week. The insets display the evolution of both the mean and standard deviation as a function of the logarithm of time after programming (in seconds), using a linear fit to predict the conductance distribution over a 10-year period. To assess the accuracy of analog MVM, a comprehensive set of non-idealities—both intrinsic to CMO/HfO x ReRAM devices and at the architecture level—is considered, including finite programming resolution with 0.2% G target acceptance range, conductance relaxation, limited ADC and DAC quantization, and IR-drop across array wires. Fig. 4 f shows the hardware-aware simulation results of the analog MVM using CMO/HfO x ReRAM cells, projected for up to 10 years from programming, compared to the expected floating-point (FP) result. The results are generated using a single 64×64 normally distributed random weight matrix and 100 normally distributed input vectors within the range [-1, 1] (see ”Methods” section ”HW-aware simulation of analog MVM” for details). Considering the input and output quantization of 6-bit and 8-bit respectively, the inset illustrates the time evolution of the root-mean-square error (RMSE) of the simulated analog MVM compared to the FP expected result. These results show that the CMO/HfO x ReRAM core enables accurate MVM operations, achieving an RMSE ranging from 0.03 at 1 second to 0.2 at 10 years after programming, compared to the ideal FP case. Fig. S6 in the Supplementary Information illustrates the impact of IR-drop and input/output quantization on the RMSE of an MVM performed on a 64×64 array. Over short time scales (within 1 hour), the primary accuracy bottleneck is the limited input/output quantization of 6-bit and 8-bit, respectively. Over longer periods, relaxation effects become the dominant source of non-ideality. In a larger 512×512 array, IR-drop emerges as the main accuracy bottleneck for analog MVM. Compared to the analog ReRAMs studied by Wan et al. [9], who report an experimentally determined RMSE of approximately 0.58 under conditions similar to those of this work, CMO/HfO x ReRAMs demonstrate a potential improvement in MVM accuracy by a factor of 20 and 3, 1 second and 10 years after programming, respectively. The excellent MVM accuracy results demonstrate the suitability of CMO/HfO x ReRAM devices for long-term AI inference applications, and lay the foundation for AI training acceleration, where short-term forward and backward MVMs are key steps. <details> <summary>x4.png Details</summary>  ### Visual Description ## Array Relaxation and Conductance Analysis ### Overview The image presents six panels (a-f) analyzing array relaxation dynamics, conductance stability, and simulation accuracy in resistive memory devices. Panels a-e focus on experimental data, while panel f presents simulation results. Key themes include temporal relaxation behavior, error quantification, and long-term stability. ### Components/Axes **Panel a**: - **X-axis**: Programmed Conductance [µS] (10-90 µS) - **Y-axis**: Probability Density (0-1.0) - **Legend**: Adjacent State Gaussian Overlap (10min): 9.6% - **Color Gradient**: Blue (low) → Red (high) probability density **Panel b**: - **X-axis**: Programmed Conductance [µS] (10-90 µS) - **Y-axis**: Standard Deviation [µS] (0-1.0) - **Markers**: - Purple circles: During Programming (Acc. Range 0.2%) - Green circles: 10 min After Programming - **Annotations**: Arrows labeled "Array Relaxation After 10 min" **Panel c**: - **X-axis**: Time after Programming [s] (log scale: 10⁰-10³) - **Y-axis**: Programmed Conductance [µS] (10-90 µS) - **Color Gradient**: Red (high G-state) → Blue (low G-state) **Panel d**: - **X-axis**: Programmed Conductance [µS] (10-90 µS) - **Y-axis**: 1h-Relaxation Error [G₁h - G_prog] [µS] (-3 to +3) - **Trendline**: Dashed black line (Avg. Error = -0.68 µS) **Panel e**: - **X-axis**: Programmed Conductance [µS] (40-60 µS) - **Y-axis**: Normalized Probability Density (0-1.0) - **Legend**: Time Intervals (1s, 1h, 1d, 1w, 10y) - **Inset Graphs**: - Top: Mean vs. Log(Time) [10y marker at 45 µS] - Bottom: Std. Dev. vs. Log(Time) [10y marker at 55 µS] **Panel f**: - **X-axis**: Expected Inner Product Output (-5 to +5) - **Y-axis**: ReRAM Inner Product Output (-5 to +5) - **Markers**: - Purple circles: Program (Prog) - Blue squares: 1s - Green diamonds: 1h - Red triangles: 10y - **Trendline**: Red dashed line (Ideal 1:1 correlation) - **Inset Graph**: RMSE vs. Log(Time) [10y marker at 10⁻¹ RMSE] ### Detailed Analysis **Panel a**: - Probability density peaks at ~45 µS (blue) and ~75 µS (red), indicating bimodal distribution. - Adjacent state overlap (9.6%) suggests partial conductance state interference. **Panel b**: - Standard deviation decreases by ~0.4 µS after 10 min (green markers vs. purple). - Lower conductance states (<30 µS) show larger relaxation effects. **Panel c**: - G-state relaxation follows exponential decay: - 90 µS → 70 µS in 1s - Stabilizes near 50 µS after 1h. **Panel d**: - Negative average error (-0.68 µS) indicates systematic underestimation of G₁h. - Errors cluster around ±1 µS for mid-range conductances (40-60 µS). **Panel e**: - Conductance stabilizes at ~50 µS after 10y (dashed black line). - Insets show: - Mean shifts from 45 µS (1s) to 55 µS (10y) - Std. Dev. decreases from 5 µS (1s) to 2 µS (10y) **Panel f**: - Strong linear correlation (R² > 0.95) between expected and observed outputs. - 10y data points deviate by <0.5 units from ideal line. - RMSE improves from 0.1 (1s) to 0.01 (10y). ### Key Observations 1. **Temporal Relaxation**: Conductance states relax toward ~50 µS across all time scales (panels a, c, e). 2. **Error Patterns**: Systematic underestimation (-0.68 µS avg.) suggests calibration requirements (panel d). 3. **Simulation Accuracy**: MVM models achieve <1% error after 10y (panel f). 4. **Bimodal Distribution**: Two dominant conductance states emerge post-programming (panel a). ### Interpretation The data demonstrates that resistive memory arrays exhibit predictable relaxation toward a stable conductance state (~50 µS) over time, with errors decreasing systematically in simulations. The 9.6% adjacent state overlap (panel a) and -0.68 µS average error (panel d) highlight the need for error-correction mechanisms in multi-state devices. The MVM simulations (panel f) validate the physical model's accuracy, showing <1% deviation after long-term operation. These findings suggest that array relaxation is both time-dependent and conductance-range specific, with implications for multi-bit storage architectures. </details> Figure 4: Conductance relaxation and MVM accuracy. a Probability density distributions of 35 conductance states approximately 10 minutes after programming. The black areas between adjacent Gaussian distributions represent the overlap of their tails. On average, an overlap of 9.6% is observed after 10 minutes. b The standard deviations of the 35 conductance states during programming (in purple) and 10 minutes after it (light blue). c Relaxation of 400 conductance states, with one device per G-state, measured 1 second and 1 hour after programming. d Relaxation error 1 hour after programming. A negative and nearly G-independent average error (dashed line) indicates that relaxation in CMO/HfO x ReRAMs tends toward a slight conductance decrease and is state-independent. e Experimental array relaxation of a representative 50 µS state, up to 1 week after programming with 0.2% G target acceptance range. Each probability density distribution is normalized to its maximum for graphical representation. The experimental data used to extract the distributions are represented as points aligned to the y=0 horizontal axis. Insets show the time dependence of the mean and standard deviation. Dashed blue lines represent the conditions during programming, once the convergence to G target is reached, while a linear fit (green dashed line) extrapolates the distribution 10 years after programming (dashed black line). f Analog MVM accuracy simulations using a 64x64 CMO/HfO x ReRAM array as a function of time after programming (indicated by different colors). The inset shows the expected RMSE compared to the ideal FP result. Experimental programming noise, conductance relaxation, limited input/output quantization and IR-drop are considered in this assessment. ### 2.3 Analog training with CMO/HfO x ReRAM core To efficiently tackle deep learning workloads, the analog AI accelerator must not only perform forward and backward passes (MVMs), but most importantly, allow for weight updates [38]. During backpropagation, the synaptic weights are modified according to the gradient of the corresponding layer. Therefore, the device conductance must be gradually modified in both positive and negative directions to represent analog weight changes. Analog CMO/HfO x ReRAM arrays not only allow for bidirectional conductance updates, but additionally enable parallel weight updating by following a stochastic open-loop pulse scheme [20, 21]. Remarkably, the parallel and open-loop update scheme significantly accelerates training compared to serial and closed-loop methods, providing efficiency gains of several orders of magnitude and advantages in system design complexity [39]. In this section, the bidirectional open-loop response of the CMO/HfO x ReRAM array, required during Tiki-Taka training, is characterized. Specifically, the analog conductance potentiation, depression and symmetry point are measured. Subsequently, the devices’ responses are statistically reproduced in the open-source ’aihwkit’ simulation platform developed by IBM [38]. Finally, this hardware-aware device model, which includes device variabilities, is used to simulate the training of representative neural networks using the AGAD learning algorithm. This novel analog training algorithm relaxes the symmetry requirements of previous Tiki-Taka versions by incorporating additional digital computations on-the-fly [23]. #### 2.3.1 Open-loop ReRAM array characterization Fig. 5 a shows the experimental conductance change of a representative CMO/HfO x ReRAM device within the array upon applying identical-voltage pulse trains with alternating polarity in batches of 400. Subsequently, a sequence of 500 pulses with alternating polarity, consisting of 1-pulse-up followed by 1-pulse-down, is applied to experimentally determine the symmetry point. The same open-loop programming scheme, with $V_{\rm set}=1.35\,\mathrm{V}$ ( $V_{\rm G}=1.4\,\mathrm{V}$ ) and $V_{\rm reset}=-1.3\,\mathrm{V}$ ( $V_{\rm G}=3.3\,\mathrm{V}$ ), each lasting 2.5 µs, is applied to all devices in the 8x4 array. The set / reset pulse width is limited by the experimental setup, although previous work has demonstrated CMO/HfO x ReRAM switching with pulses as short as $60\,\mathrm{ns}$ [25]. Due to inter-device (device-to-device) and intra-device (cycle-to-cycle) variabilities, the experimental response of each device to a given number of identical pulses exhibits some level of variability (see Fig. S7 in the Supplementary Information). Therefore, for each pulse, a Gaussian distribution of the measured conductance states among the devices is extracted. For statistical relevance, Fig. 5 b shows the experimental standard deviation of the array response to the open-loop scheme as a function of the pulse number, represented in grey. To realistically assess the accuracy of analog training with CMO/HfO x ReRAM devices, the key figures of merit of the device training characterization—such as the number of states, the symmetry point skew, and the noise-to-signal ratio (NSR)—are first extracted from experimental data, as defined below. $$ \displaystyle\mathrm{N}_{\rm states}=\frac{G_{\rm max}-G_{\rm min}}{\overline{ \Delta G_{\rm sp}}} \tag{1} $$ $$ \displaystyle\mathrm{SP}_{\rm skew}=\frac{G_{\rm max}-\overline{G_{\rm sp}}}{G _{\rm max}-G_{\rm min}} \tag{2} $$ $$ \displaystyle\mathrm{NSR}=\frac{\sigma_{\Delta G_{\rm sp}}}{\overline{\Delta G _{\rm sp}}} \tag{3} $$ $G_{\rm max}$ and $G_{\rm min}$ represent the maximum and minimum values extracted from the full conductance swings, while $\overline{G_{\rm sp}}$ , $\overline{\Delta G_{\rm sp}}$ and $\sigma_{\Delta G_{sp}}$ denote the values of the mean conductance, mean conductance update and standard deviation of the conductance update at the symmetry point during the 1-pulse-up, 1-pulse-down procedure, respectively. Fig. 5 c shows the experimental Gaussian distributions of these metrics for the 32 devices within the array. The results indicate an average of 22 states, with a range from 16 to 33. A shift in the $G_{\rm sp}$ (or SP skew) of 61% is measured, reflecting a negative trend in the device asymmetry where the down response is steeper than the up response. An average NSR of 90% among the devices is obtained, demonstrating the capability to discriminate between pulses up and down around the symmetry point. This parameter reflects the intrinsic noise on the device’s response under identical conditions, highlighting an intra-device variation [38]. Previous studies on similar CMO/HfO x ReRAM systems [24] extracted these metrics from isolated 1R devices using an optimized open-loop scheme tailored to each device. In contrast, this work demonstrates for the first time that a single open-loop identical pulse scheme enables reliable operation of the entire CMO/HfO x 1T1R array, ensuring consistent performance across the array. <details> <summary>x5.png Details</summary>  ### Visual Description ## Chart/Diagram Type: Analog Switching Characteristics of a ReRAM Device (Open-Loop) ### Overview The image presents three interconnected technical visualizations analyzing a ReRAM (Resistive Random-Access Memory) device's behavior. Section **a** shows analog switching characteristics, **b** depicts array-level statistical responses, and **c** summarizes experimental metrics for Tiki-Taka training. --- ### Components/Axes #### Section a: Analog Switching Characteristics - **X-axis**: Pulse Number (0–2100) - **Y-axis**: Conductance [μS] (logarithmic scale: 0–100) - **Legend**: - Red: Potentiation (1.35V, 2.5μs) - Blue: Depression (1.3V, 2.5μs) - **Inset**: Histogram of conductance after 1200 pulses (G₁₂₀₀) with ±σ shading. #### Section b: Array-Level Open-Loop Statistical Response - **X-axis**: Pulse Number (0–2100) - **Y-axis**: Conductance [μS] (logarithmic scale: 0–100) - **Legend**: Array experimental data (black line with ±σ shading). - **Inset**: Histogram of conductance after 1200 pulses (G₁₂₀₀) with ±σ shading. #### Section c: Experimental Array Metrics for Tiki-Taka Training - **Histograms**: 1. **Number of States**: X-axis (0–40), mean = 22. 2. **Symmetry Point Skew (%)**: X-axis (20–110), mean = 61%. 3. **Noise to Signal Ratio (%)**: X-axis (70–110), mean = 90%. - **Formulas**: - N_states = (G_max - G_min) / ΔG_sp - SP_skew = (G_max - G_sp) / G_max - NSR = σΔG_sp / ΔG_sp --- ### Detailed Analysis #### Section a - **Potentiation (Red)**: Conductance increases sharply to ~100 μS at ~800 pulses, then stabilizes. - **Depression (Blue)**: Conductance drops to ~10 μS at ~1600 pulses, then stabilizes. - **Key Labels**: - G_max ≈ 100 μS (potentiation peak). - G_min ≈ 10 μS (depression trough). - ΔG_sp ≈ 90 μS (difference between G_max and G_sp). - G_sp ≈ 10 μS (conductance at symmetry point). #### Section b - **Array Data**: Conductance fluctuates between ~10 μS and ~100 μS, with ±σ shading indicating variability. - **Inset Histogram**: Conductance distribution after 1200 pulses is approximately normal (G₁₂₀₀ ≈ 50 μS, ±σ ≈ ±10 μS). #### Section c - **Number of States**: Bimodal distribution with mean = 22. - **Symmetry Point Skew**: Right-skewed distribution (mean = 61%). - **Noise to Signal Ratio**: Left-skewed distribution (mean = 90%). --- ### Key Observations 1. **Conductance Switching**: Potentiation and depression create distinct conductance states (G_max ≈ 100 μS, G_min ≈ 10 μS). 2. **Statistical Variability**: Shaded regions in **b** indicate device-to-device or batch-to-batch variability. 3. **Training Metrics**: - Tiki-Taka training increases the number of conductance states (mean = 22). - Symmetry point skew (61%) and noise-to-signal ratio (90%) suggest trade-offs between precision and noise. --- ### Interpretation - **ReRAM Behavior**: The device exhibits bistable conductance switching, critical for memory applications. - **Array-Level Variability**: The ±σ shading in **b** highlights manufacturing or operational inconsistencies. - **Tiki-Taka Training**: The metrics in **c** quantify how training affects device performance: - Increased states (N_states) improve memory capacity. - High skew (61%) and noise (90%) may limit reliability. - **Trade-offs**: Optimizing for one metric (e.g., N_states) may degrade others (e.g., NSR). --- **Note**: All values are approximate, derived from visual inspection of axis scales and legend labels. Uncertainties (e.g., ±σ) are inferred from shaded regions and histogram spreads. </details> Figure 5: Open-loop array characterization for on-chip training. a Bidirectional accumulative response and symmetry point of a representative device in the array. The top inset shows the open-loop identical pulse scheme used for the synaptic potentiation (red) and depression (blue). A conceptual illustration of the 8x4 CMO/HfO x ReRAM array is depicted on the left. b Array statistical open-loop response to identical pulses. The grey area represents the standard deviation of the experimental Gaussian distributions, each corresponding to a specific pulse number. The inset shows a representative example of the experimental G-distribution at pulse number 1200. The raw data can be found in Figure S9 of the Supporting Information. c The experimental probability densities of N states, SP skew and NSR, respectively. The experimental data used to extract the distributions are represented as points aligned along the y=0 horizontal axis. #### 2.3.2 Tiki-Taka training simulations To perform realistic hardware-aware training simulations, the experimental device response is reproduced on software using the generalized soft bounds model implemented in the ’aihwkit’ [40], which better captures the bidirectional resistive switching behavior (see Fig. S8 in Supplementary Information) and accounts for intra- and inter-device variabilities (see cycle-to-cycle and device-to-device variations in Fig. 6 a). Additionally, Gaussian distributions are modelled based on parameters extracted from device characterization ( $G_{\rm max}$ , $G_{\rm min}$ , $\Delta G_{\rm sp}$ , NSR, SP skew) to account for device-to-device variability observed in the experimental characterization (see ”Methods” section ”Intra and inter-device variability” for details). This Gaussian fitting approach allows defining various device presets—characterized by the same model but with different parameter settings—to represent the synapses across the neural network. A realistic simulation setup is obtained by exclusively considering experimentally obtained parameters to reproduce the device trace (see ”Methods” section ”Generalized soft bounds model” for details). The device model is defined based on the observed conductance window and number of states, without assuming asymptotic behavior for an infinite number of pulses. This prevents overestimation of both the conductance window and the number of states (material states), enhancing the fidelity of the simulation. To validate analog training with CMO/HfO x ReRAM technology, a 3-layer fully connected (FC) neural network was trained on the MNIST dataset for image classification. In addition, the impact of the device’s number of states, asymmetry, and noise-to-signal ratio on accuracy and convergence time is evaluated by simulating identical networks in which each property is individually enhanced, while keeping the others fixed at the experimentally derived values. Literature has shown that these device characteristics critically influence the convergence of analog training algorithms [23]. Therefore, this method assesses the deviation of the current CMO/HfO x ReRAM device properties from the ideal analog resistive device scenario. Moreover, to show the scalability of the CMO/HfO x ReRAM technology to more computationally-intensive tasks, such as time series processing, a 2-layer long short-term memory (LSTM) network was trained on War and Peace text sequences to predict the next token. Each network is initially trained using conventional stochastic gradient descent (SGD) based backpropagation with 32-bit FP precision, serving as the baseline performance. Fig. 6 b illustrates the accuracy per epoch for the FP-baseline trained with SGD (in green) and the analog network trained using AGAD, evaluated under four different parameter settings: (1) properties extracted from the experimental array (in yellow), (2) reduced NSR to 20% (in red), (3) average of N states = 100 states (in blue), and (4) zero average device asymmetry (in orange). Using symmetrical device presets, i.e. with an average SP skew of 50%, improves accuracy by 0.7% with respect to analog training with CMO/HfO x ReRAM experimentally derived configuration (96.9%), landing an accuracy of 97.6%, a 0.7% lower than the FP-SGD baseline (98.3%). The other two configurations show less performance improvement, indicating more resilience of the AGAD-training to device’s N states and NSR. Additionally, a 2-layer LSTM network with 64 memory states each (see Fig. 6 c), is trained with the experimentally obtained configuration. The performance is measured using the exponential of the cross-entropy loss, i.e. the test perplexity metric, which quantifies the certainty of the token prediction. Results in Fig. 6 d demonstrate the capabilities of the CMO/HfO x ReRAM technology on more complex network architectures, such as LSTMs, and computationally demanding tasks, exhibiting performance comparable to the FP-equivalent, with an approximate 0.7% difference in test perplexity. <details> <summary>x6.png Details</summary>  ### Visual Description ## Line Graph: Generalized Soft Bounds Device Model ### Overview A line graph showing weight fluctuations across four devices (Dev1–Dev4) over 2100 pulses. The y-axis ranges from -1 to 2, with overlapping lines indicating device-specific weight variations. ### Components/Axes - **X-axis**: Pulse Number (0–2100) - **Y-axis**: Weight (-1 to 2) - **Legend**: - Dev1: Dark blue diamonds - Dev2: Teal diamonds - Dev3: Green diamonds - Dev4: Yellow diamonds ### Detailed Analysis - **Dev1 (Dark Blue)**: Starts at ~1.5, dips to ~0.5 at pulse 800, then rises to ~1.8 by pulse 2100. - **Dev2 (Teal)**: Peaks at ~1.8 near pulse 0, drops to ~0.2 at pulse 800, then stabilizes at ~1.6. - **Dev3 (Green)**: Begins at ~1.2, fluctuates between ~0.8 and ~1.5, ending at ~1.4. - **Dev4 (Yellow)**: Starts at ~0.9, dips to ~0.3 at pulse 800, then rises to ~1.3. ### Key Observations - All devices exhibit periodic dips around pulse 800. - Dev1 and Dev2 show the most pronounced fluctuations. - Dev4 has the smallest amplitude in weight changes. ### Interpretation The graph suggests device-specific weight dynamics under a generalized model. The synchronized dip at pulse 800 may indicate a shared response to a stimulus or system reset. Dev1’s final weight (~1.8) implies higher sensitivity compared to others. --- ## Bar Chart: 3FC MNIST Training ### Overview A bar chart comparing test accuracy (%) of five training methods over 80 epochs. The y-axis ranges from 90% to 100%. ### Components/Axes - **X-axis**: Epochs (0–80, labeled "a.u.") - **Y-axis**: Test Accuracy (%) - **Legend**: - CMO/HFOₓ exp. array: Yellow diamonds - NSR down to 20%: Red circles - Nstates up to 100: Blue squares - Symmetry (SP_skew 50%): Orange crosses - SGD: Green pluses - FP-baseline: Green pluses (baseline) ### Detailed Analysis - **CMO/HFOₓ exp. array**: Peaks at ~98% by 80 epochs. - **NSR down to 20%**: Reaches ~97% by 80 epochs. - **Nstates up to 100**: Stabilizes at ~96.5%. - **Symmetry (SP_skew 50%)**: ~97.5% at 80 epochs. - **SGD**: ~94% at 80 epochs. - **FP-baseline**: ~98% (constant across epochs). ### Key Observations - CMO/HFOₓ exp. array and FP-baseline achieve the highest accuracy. - Symmetry (SP_skew 50%) outperforms Nstates and NSR. - SGD lags significantly behind other methods. ### Interpretation CMO/HFOₓ exp. array and FP-baseline demonstrate superior convergence, suggesting robust training dynamics. The FP-baseline’s consistency implies it serves as a strong benchmark. SGD’s lower performance highlights its limitations in this context. --- ## Diagram: LSTM Network Trained Using CMO/HFOₓ Statistical Array Data ### Overview A block diagram of an LSTM network processing input tokens ("The", "man", "walks", etc.) to output "street". ### Components 1. **Input Layer**: - Tokens converted to one-hot encoding (87xN). 2. **LSTM Layers**: - **LSTM1**: 64 hidden units, 87x64xN input. - **LSTM2**: 64 hidden units, 64x64xN input. 3. **Fully Connected (FC) Layer**: 64x87x1 output. 4. **Output**: "street" (87x1). ### Flow Input → One-Hot Encoding → LSTM1 → LSTM2 → FC → Output. ### Key Observations - The network uses two LSTM layers for sequential processing. - The FC layer maps hidden states to output tokens. ### Interpretation This architecture is designed for sequence-to-sequence tasks, leveraging LSTM’s memory capabilities. The one-hot encoding ensures discrete token representation, while the FC layer finalizes predictions. --- ## Line Graph: LSTM Training ### Overview A line graph comparing test perplexity (1–5) of three methods over 100 epochs. ### Components/Axes - **X-axis**: Epochs (0–100, labeled "a.u.") - **Y-axis**: Test Perplexity - **Legend**: - AGAD: Yellow diamonds - CMO/HFOₓ exp. array: Orange crosses - FP-baseline: Green pluses ### Detailed Analysis - **AGAD**: Starts at ~3.5, decreases to ~2.0 by 100 epochs. - **CMO/HFOₓ exp. array**: Drops from ~3.0 to ~2.2. - **FP-baseline**: Remains flat at ~1.2. ### Key Observations - AGAD shows the steepest decline in perplexity. - FP-baseline maintains the lowest perplexity throughout. ### Interpretation AGAD’s rapid improvement suggests effective training dynamics. FP-baseline’s stability indicates it may represent an optimized or pre-trained model. The divergence between AGAD and FP-baseline highlights differences in training strategies. </details> Figure 6: Device model and on-chip training simulations. a Device presets generated using the generalized soft bounds model with experimentally extracted parameters of CMO/HfO x devices, including inter- and intra-device variabilities. b Training simulations of a 3-layer fully-connected neural network on MNIST (235K parameters), using 32-bit FP precision trained on SGD (in green). Analog training simulations were performed using AGAD considering the empirical distribution of the parameters (in yellow), enhanced NSR (in red), increased N states (in blue), and symmetrical device configurations (in orange). c LSTM network architecture for text forecasting on the War and Peace dataset (79K parameters). The architecture considers a sequence length of 100 tokens and accounts for 2 layers with 64 hidden units. d Training results of the FP baseline (in green) and the analog training with AGAD on the experimental device configuration (in yellow). The training setup can be found in the Supporting Information. ## 3 Discussion An all-in-one technology platform based on analog filamentary CMO/HfO x ReRAM devices is presented. This platform addresses critical challenges in modern digital AI accelerators by overcoming the physical separation between memory and compute units. It enables the execution of forward and backward MVMs, along with weight updates and gradient computations, directly on a unified analog in-memory platform with $O(1)$ time complexity. This all-in-one approach fundamentally differs from DNN inference-only [9] and training-only [24, 41] analog accelerators. In inference-only accelerators, DNN weights are trained in software (i.e., off-chip) using traditional digital CPUs or GPUs and then programmed once onto the analog AI hardware accelerator. In training-only accelerators, the long-term retention capabilities and overall MVM accuracy for large array tiles are not assessed. In this work, a novel all-in-one analog computing platform, capable of both on-chip training and inference acceleration, is unveiled. The CMO/HfO x ReRAM devices are integrated in the BEOL of a NMOS transistor platform in a scalable 1T1R array architecture. The highly reproducible forming step demonstrates compatibility with NMOS rated for $\mathrm{3.3\,V}$ operation, while the uniform quasi-static 8W-cycling characteristics, achieved with voltage amplitudes of less than $\pm$ $\mathrm{1.5\,V}$ , exhibit a significant conductance window and a low off-state. The multi-bit capability of more than 32 states (5 bits), distinguishable after 10 minutes with less than 10% overlap error, is experimentally demonstrated using an identical-pulse closed-loop scheme. The characterization of the weight transfer reveals record-low programming noise ranging from $\mathrm{10\,nS}$ to $\mathrm{100\,nS}$ , more than one order of magnitude lower than that of other memristive technologies targeting similar conductance ranges [34, 35, 36]. Each conductance distribution exhibits a state-independent relaxation process over time, characterized by a slight shift of the mean toward lower conductance and an increase in the standard deviation. This independence of the relaxation process from the target conductance is advantageous for implementing effective compensation schemes in the future. Realistic MVM simulations on a 64x64 array tile, considering CMO/HfO x ReRAM device non-idealities such as finite weight transfer resolution, conductance relaxation, limited input/output quantization, and IR-drop across array wires, show an RMSE as low as 0.2 compared to the ideal FP-case, even 10 years after programming. This demonstrates that the CMO/HfO x ReRAM devices improve analog MVM accuracy by a factor of 20 and 3 compared to the state of the art [9], 1 second and 10 years after programming, respectively. Although this study was performed at room temperature, previous characterization of a similar CMO/HfO x ReRAM stack demonstrated the thermal stability of the analog states at high temperature (less than 4% drift after 72 hours at 85 °C) [24]. Future studies will focus on incorporating the experimental read noise of CMO/HfO x ReRAM devices, characterized between 0.2% and 2% of G target within a similar conductance range as used in this work [25], into MVM accuracy simulations. Although read noise is not included in the MVM simulations of this study, no significant additional drop in MVM accuracy is anticipated. In fact, the magnitude of read noise is much smaller than that of the relaxation process and of the effect of reduced input/output quantization, which dominate the RMSE on different timescales. Furthermore, simulation results demonstrate the suitability of CMO/HfO x ReRAM technology for large 512x512 array, with the IR-drop expected to become the primary accuracy bottleneck in this case. Finally, the electrical response of the CMO/HfO x ReRAM array to an open-loop scheme with identical pulses demonstrates the viability of this technology for on-chip training applications. A realistic device model, accounting for both inter- and intra-device variability, is derived from experimental data. Table 1 benchmarks the representative device model used in this work on the MNIST dataset against other approaches, highlighting its high fidelity in reproducing experimental device responses. Table 1: Device model benchmarking: from simplified approaches to realistic non-ideality modeling | Ti/HfO x [41] | Not-included | exp. states Measured number of analog states during open-loop device characterization. | BEOL array | TTv2 | Medium | 90.5 % | | --- | --- | --- | --- | --- | --- | --- | | Ta/TaO x [41] | Not-included | exp. states Measured number of analog states during open-loop device characterization. | BEOL array | TTv2 | Medium | 96.4 % | | TaO x /HfO x [24] | included | material states The asymptotic number of states under an infinite number of pulses. | Single ReRAMs | TTv2 | Medium | 97.4 % | | CMO x /HfO x This work. | included | exp. states Measured number of analog states during open-loop device characterization. | BEOL array | AGAD | High | 96.9 % | The impact of the device’s number of states, asymmetry and noise-to-signal ratio on training accuracy using the AGAD algorithm on MNIST is evaluated. This analysis demonstrates that, with the current device’s experimental properties, AGAD analog training achieves 96.9% accuracy, comparable to the ideal FP-baseline of 98.3%. To further improve analog training performance and bring results closer to the software equivalent, the key metric to enhance in the device is the symmetry. Finally, the on-chip analog training capabilities of the CMO/HfO x ReRAM technology are demonstrated on a more complex 2-layer LSTM network, showing comparable performance to its floating-point equivalent. In conclusion, the novel CMO/HfO x ReRAM all-in-one technology platform presented in this work lays the foundation for efficient and versatile analog chips capable of combining both training and inference capabilities, enabling autonomous, energy-efficient, and adaptable AI systems. ## 4 Methods ### 4.1 Device fabrication The CMO/HfO x ReRAM array is based on 1T1R unit cells. In this configuration, the bottom electrode of the ReRAM device is connected in series to the drain of an n-type metal–oxide–semiconductor (NMOS) selector transistor. The transistor blocks sneak paths and ensures current compliance during electro-forming and programming of the ReRAM device. The NMOS transistors, rated for $\mathrm{3.3\,V}$ operation, are fabricated using a standard $\mathrm{130\,nm}$ foundry process with copper BEOL interconnects. The ReRAM devices are integrated on metal-8 layer. To prevent the oxidation of the copper vias during the ReRAM stack deposition, the $\mathrm{70\,nm}$ thick silicon nitride (SiN x) passivation layer from the foundry is used as a protective layer. On top of that, a $\mathrm{20\,nm}$ thick titanium nitride (TiN) bottom electrode and a $\mathrm{4\,nm}$ thick hafnium oxide (HfO x) layers are deposited by Plasma-Enhanced Atomic Layer Deposition (PEALD) process at 300 °C, while maintaining vacuum conditions to avoid oxidation of the TiN layer. Subsequently, a stack of layers consisting of a $\mathrm{20\,nm}$ thick conductive metal-oxide (CMO), a $\mathrm{20\,nm}$ thick titanium nitride (TiN), and a $\mathrm{50\,nm}$ thick tungsten (W) is deposited by sputtering and patterned through a lithography step. A $\mathrm{100\,nm}$ thick silicon oxide (SiO x) layer is sputtered as passivation. The passivation layer is then patterned to expose the W top electrode and the copper via in the metal-8 layer beneath the bottom electrode. The ReRAM fabrication is completed using a titanium/gold lift-off process. In this approach, the TiN bottom electrode is connected to the metal-8 via through its vertical sidewalls using gold. The ReRAM BEOL patterning steps are performed through mask-based photolithography performed on a 6 $\times$ 6 mm 2 die issued from a Multi Project Wafer (MPW). The area of the CMO/HfO x ReRAM devices presented in this work is 12 $\times$ 12 µm 2. Previous studies on CMO/HfO x ReRAM devices have demonstrated scalability down to 200 $\times$ 200 nm 2 [24, 26, 25]. Due to their filament-type nature, the performance of the ReRAM devices presented in this work is expected to remain similar for smaller areas. ### 4.2 ReRAM forming modelling A 3D FEM of the CMO/HfO x ReRAM device, after the forming event, is used to simulate electronic transport by solving the continuity (4) and the Joule-heating (5) equations in steady state: $$ \displaystyle\nabla\cdot J_{\rm e}=\nabla\cdot(\sigma(-\nabla V)=0 \tag{4} $$ $$ \displaystyle\nabla\cdot(-k\nabla T)=J_{\rm e}\cdot E=Q_{\rm e} \tag{5} $$ where $J_{\rm e}$ is the electric current density, $\sigma$ the electrical conductivity, $V$ the electric potential, $k$ the thermal conductivity and $Q_{\rm e}$ the heat source due to Joule heating. From the fit of the experimental array forming data in the low-voltage linear regime (from 0 to $0.2\,\mathrm{V}$ ), an average filament radius of $11\,\mathrm{nm}$ is extracted. The electrical and thermal conductivities of the materials in the ReRAM stack are taken from literature [26], by considering $\sigma_{\mathrm{CMO}}=5\,\mathrm{S/cm}$ and $k_{\mathrm{CMO}}=4\,\mathrm{W/mK}$ for the CMO layer used in this work. During the subsequent negative voltage sweep, the electrical conductivity of the CMO layer was used as a fitting parameter to model the radial redistribution of defects within the layer. Using experimental array data in the low-voltage linear regime (from 0 to $\mathrm{-0.2\,V}$ ), the resulting CMO electrical conductivity is $37\,\mathrm{S/cm}$ . Fig. S1 in Supplementary Information shows the results of the simulations. ### 4.3 ReRAM forming voltage extraction The forming voltage of each 1T1R cell ( $V_{\mathrm{forming}}^{\mathrm{1T1R}}$ ) is defined as the voltage required to trigger the highest current increase ( $\max\left(\frac{dI}{dV}\right)$ ) during the quasi-static voltage sweep from 0 to $3.6\,\mathrm{V}$ (see Supplementary Information Fig. S2 a). The corresponding current is defined as the forming current ( $I_{\mathrm{forming}}^{\mathrm{1T1R}}$ ) (see Supplementary Information Fig. S2 b). Being the transistor driven by a constant $V_{\mathrm{G}}=1.2\,\mathrm{V}$ , it acts as a series resistor in the triode region before the forming event, when the ReRAM stack is highly insulating. After the forming event, when a conductive filament is created in the ReRAM device, the transistor ensures current compliance in the saturation region. The resistance of the transistor in the triode region at $V_{\mathrm{G}}=1.2\,\mathrm{V}$ is measured to be $R_{\mathrm{DS}}\approx 0.8\,\mathrm{k\Omega}$ (see Supplementary Information Fig. S2 c). Therefore, for each 1T1R cell, the actual ReRAM forming voltage is computed as $V_{\mathrm{forming}}^{\mathrm{ReRAM}}=V_{\mathrm{forming}}^{\mathrm{1T1R}}-R_{ \mathrm{DS}}^{\mathrm{triode}}\cdot I_{\mathrm{forming}}^{\mathrm{1T1R}}$ and reported in Fig. 2 c. ### 4.4 Analytical ReRAM transport modelling In the 1T1R cell, the electronic current $I_{\rm e}$ is modelled as a trap-to-trap tunneling process within the CMO layer, as described in equation (6), following the model proposed by Mott and Gurney [42]. This model accounts for electron-hopping conduction across an energy barrier $\Delta E_{\rm e}$ , which remains uniform in all directions when there is no electric field applied. However, when an electric field is introduced, it modifies the energy barrier by $\mp$ $ea_{\rm e}E$ /2 for forward (backward) jumps, leading to a reduction (increase) in the barrier height. $$ \displaystyle I_{\rm e}^{\rm Mott-Gurney}=2Aea_{\rm e}\nu_{\rm 0,e}N_{\rm e} \exp{(\frac{-\Delta E_{\rm e}}{k_{\rm B}T})}\sinh{(\frac{a_{\rm e}eE}{2k_{\rm B }T})} \tag{6} $$ In equation (6), $e$ is the elementary charge, $k_{\rm B}$ is the Boltzmann’s constant, $a_{\rm e}$ is the hopping distance, $\nu_{\rm 0,e}$ is the electron attempt frequency, $N_{\rm e}$ is the density of electronic defect states in the sub-band of the CMO layer, $\Delta E_{\rm e}$ is the zero-field hopping energy barrier, $T$ and $E$ are the local temperature and electric field, respectively, and $A=\rm\pi\it r_{\rm CF}^{\rm 2}$ , $r_{\rm CF}$ being the filament radius, is the cross-sectional area of the filament at the interface with the CMO layer. The temperature and electric field in the CMO layer, for both LRS and HRS, are simulated by solving equations (4) and (5), while accounting for the experimental I-V non-linearity (see Supplementary Fig. S4 for details). The trap-to-trap tunneling parameters ( $N_{\rm e}$ , $\Delta E_{\rm e}$ , $a_{\rm e}$ ) are extracted from the fit using the same approach as described in previous works [26, 31]. ### 4.5 Identical-pulse closed-loop scheme The procedure begins with a quasi-static voltage sweep from 0 to $-1.5\,\mathrm{V}$ to reset each cell within the array to the HRS. Subsequently, a closed-loop scheme is initiated, which iteratively repeats the following two steps until convergence to G target within an acceptance range: (1) read the conductance of the ReRAM cell, and (2) if the measured value is below (above) the target conductance, apply a set (reset) programming pulse. During this iterative process, the cell conductance may fluctuate multiple times before eventually reaching the acceptance range. Starting from the HRS, this procedure is applied to the CMO/HfO x ReRAM array to sequentially program 35 representative conductance levels, ranging from approximately 10 µS to 90 µS, using acceptance ranges of both 0.2% G target and 2% G target. Unlike the conventional incremental-pulse closed-loop technique previously used for ReRAM [9, 43], where the amplitudes of set and reset pulses are gradually increased to achieve convergence, this work employs an identical-pulse closed-loop scheme to simplify the pulse generation circuitry design, using only two fixed amplitude values for the set ( $1.35\,\mathrm{V}$ or $1.5\,\mathrm{V}$ ) and two for the reset ( $-1.3\,\mathrm{V}$ or $-1.5\,\mathrm{V}$ ) pulses. Specifically, depending on G target, three ranges are used: from approximately 10 µS to 30 µS with $V_{\rm set}=1.35\,\mathrm{V}$ and $V_{\rm reset}=-1.5\,\mathrm{V}$ ; from 30 µS to 60 µS $V_{\rm set}=1.35\,\mathrm{V}$ and $V_{\rm reset}=-1.3\,\mathrm{V}$ ; and from 60 µS to 90 µS $V_{\rm set}=1.5\,\mathrm{V}$ and $V_{\rm reset}=-1.3\,\mathrm{V}$ . Fig. S5 b in Supplementary Information shows the flowchart of the identical-pulse closed-loop technique used in this work. The set / reset pulse width is fixed at 2.5 µs due to setup limitations, even though previous work has demonstrated CMO/HfO x ReRAM switching with pulse width as short as $60\,\mathrm{ns}$ [25]. The reading pulse amplitude and width are $V_{\rm read}=0.2\,\mathrm{V}$ and 300 µs, respectively. During the set, reset, and read operations of each 1T1R cell, the transistor’s gate voltage is controlled with constant values of $V_{\rm G}$ equal to $1.4\,\mathrm{V}$ , $3.3\,\mathrm{V}$ , and $3.3\,\mathrm{V}$ , respectively. ### 4.6 HW-aware simulation of analog MVM The ’aihwkit’ [44] simulation tool was used to perform MVM assessments including non-ideal behaviors and noise, and their effect on the computation accuracy with respect to floating-point operations. The MVM simulation included the exhibited programming noise, conductance relaxation, input and output quantization, and IR-drop across array wires. The ’aihwkit’ allows to configure such noisy effects for dedicated memristive devices such as PCM by Nandakumar et al. [45] and ReRAM by Wan et al. [9]. Therefore, a unique phenomenological noise model for CMO/HfO x ReRAM devices for inference is developed to incorporate into the simulation both the characterized programming noise and conductance relaxation. Additionally, input and output are quantized with 6-bit and 8-bit resolution, respectively, and the IR-drop is considered, with 100 µS as the maximum ReRAM conductance level and a default segment wire resistance of 0.35 $\Omega$ . #### 4.6.1 Modelling the programming noise For a target conductance G target, the device’s programmed conductance is defined as the target value plus normally distributed noise with a standard deviation $\sigma_{\rm prog}$ , which is a function of G target. As depicted in Fig. 3 e, the programming noise ( $\sigma_{\rm prog}$ ) of the CMO/HfO x ReRAM devices is statistically described by a first-order polynomial equation for a given acceptance range. The polynomial coefficients for acceptance ranges of 2% and 0.2% of G target are extracted from the characterization and introduced into the simulation environment. To assess the effects of the programming noise, each weight in the normalized matrix (ranging from [-1, 1]) is mapped to its corresponding conductance value (within the range [9, 89] µS from Fig. 3 a), and is then further adjusted by the programming noise described by the extracted linear functions. Therefore, the MVM accuracy can be assessed immediately after programming ( $t=0$ ), see Fig. 4 f. #### 4.6.2 Modelling the conductance relaxation After programming, the conductance levels exhibit relaxation over time, as shown in Fig. 4. Unlike previous ReRAM drift characterizations reported by Wan et al. [9] the observed relaxation in CMO/HfO x ReRAM is approximately independent of the initial programmed conductance. Consequently, a new modelling approach in the ’aihwkit’ is needed to accurately simulate the conductance relaxation effect, which differs from the methods derived from previous literature on ReRAM [9]. The conductance relaxation mean and standard deviation are modelled independently of G target and solely as a function of time after programming. The coefficients of the first-order polynomials describing the time dependence of both the mean and standard deviation of the programmed conductance are incorporated into the simulation environment to estimate conductance variations at any given inference time. By doing so, the MVM accuracy can be estimated after a period of time up to 10 years. ### 4.7 HW-aware simulation of analog training #### 4.7.1 Generalized soft bounds model The generalized soft bounds model (SBM) selection was based on the observed characteristics of the potentiation and depression since the devices did not strictly exhibit thorough saturation at the upper and lower boundaries (see Fig. S8 in Supplementary Information). The generalized SBM incorporates a tunable scale exponent ( $\gamma$ ) that describes abrupt and gradual trends toward the maximum and minimum conductance levels. This exponent parameter also varies depending on the conductance update direction. Therefore, the analytical expression of the generalized SBM implemented in the ’aihwkit’ includes an asymmetry factor ( $\gamma_{\rm up\_down}$ ) to account for this behavior [38]. However, these two parameters do not have a direct physical equivalence, and therefore, cannot be derived from experimental traces. Hereby, $\gamma$ and $\gamma_{\rm up\_down}$ are obtained for each device through an independent linear fitting of the generalized SBM to the experimental response. In addition to the analytical parameters of the generalized SBM, devices in the ’aihwkit’ are defined by a set of parameters that can be extracted from experimental traces. More precisely, the empirical maximum and minimum conductance, minimum conductance step size and its standard deviation, and the asymmetry between up and down response are considered ( $G_{\rm max}$ , $G_{\rm min}$ , $\Delta G_{\rm sp}$ , $\sigma_{\Delta G_{\rm sp}}$ , and $up\_down$ ). More details on the $up\_down$ parameter are provided in the Supplementary Information. In this regard, each simulated device is defined by 6 parameters: four empirically obtained ( $G_{\rm max}$ , $G_{\rm min}$ , $\Delta G_{\rm sp}$ and $up\_down$ ) and two analytically modelled from SBM linear fitting ( $\gamma$ and $\gamma_{\rm up\_down}$ ). #### 4.7.2 Intra and inter-device variability By extracting the standard deviation of the minimum conductance step size ( $\sigma_{\Delta G_{\rm sp}}$ ) from the experimental traces and incorporating it into the simulation’s device model, the device response intrinsically includes noise from cycle to cycle. This provides a realistic device behavior with intra-device variability. Furthermore, the network devices shall include inter-device variabilities to perform physically accurate simulations. To achieve this, two multi-variate Gaussian distributions, G 1 and G 2, are created (see Fig. S9 in Supplementary Information). G 1 is extracted from the experimentally obtained parameters: N states (which accounts for variations across devices in the G-range and step) and SP in the normalized G-range, whereas G 2 is fitted to the analytical model parameters obtained from the fitted generalized SBM ( $\gamma$ and $\gamma_{\rm up\_down}$ ). Therefore, variables from G 1 showed statistical independence from those of G 2. New device instances are independently sampled from the two Gaussian distributions to represent synapses on the DNN layers. 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Acknowledgements The authors acknowledge the Binnig and Rohrer Nanotechnology Center (BRNC) at IBM Research Europe - Zurich. Special thanks go to Jean-Michel Portal, Eloi Muhr and Dominique Drouin for their contributions to the design of the NMOS transistors used in this work. The authors also extend their gratitude to Stephan Menzel for the fruitful discussions and to Ralph Heller for his assistance in wire-bonding the chip. This work is funded by SNSF ALMOND (grantID: 198612), by the European Union and Swiss state secretariat SERI within the H2020 MeM-Scales (grantID: 871371), MANIC (grantID: 861153), PHASTRAC (grantID: 101092096) and CHIST-ERA UNICO (20CH21-186952) projects. Author contributions Conceptualization: D. F. F. and V. B.; hardware fabrication: D. F. F. and L. B. L.; electrical characterization: D. F. F, W. C., T. S., F. H., physical simulations: D. F. F.; inference and training simulations: V. C., D. F. F.; NMOS transistor design : N. G., F. A.; result interpretation: D. F. F., V. C., W. C., V. B., M. G., A. L. P. and B. J. O., supervision: V. B. and B. J. O.; manuscript writing: D. F. F., V. C.; data curation: D. F. F., V. C. and V. B.; manuscript review and editing: all authors; funding acquisition: B. J. O. and V. B. Competing interests The authors declare no competing interests. Data availability The data that support the plots within this paper and other findings of this study are available from the corresponding authors upon reasonable request. Code availability The repositories containing the source codes used in this work for analog inference simulations and CMO/HfO x ReRAM noise model can be found at this link and this link, respectively. ## Supplementary Information <details> <summary>x7.png Details</summary>  ### Visual Description ## Technical Diagram Analysis: Device Structure and Electrical Characteristics ### Overview The image presents a multi-part technical analysis of a nanoscale electronic device, combining structural diagrams (a-b) with electrical characterization graphs (c-d). The device appears to be a thin-film transistor or memory element with layered dielectric and conductive components. ### Components/Axes **a) Device Bird's-Eye View** - Dimensions: 200nm x 280nm - Structure: Square geometry with central void - Key components: Not explicitly labeled in this view **b) Device y-z Cross-Section** - Layer stack (top to bottom): 1. SiO₂ (50nm) 2. TiN (20nm) 3. CMO (20nm) 4. HfOₓ (4nm) 5. CF (conductive filament) 6. TiN (20nm) 7. SiO₂ (50nm) - Interface labels: CF (conductive filament) at bottom **c) Filament Radius Fit Graph** - Axes: - X: Voltage₁TIR (V) from -1.4 to 3.6V - Y: Current₁TIR (A) from 10⁻⁹ to 10⁻³A - Legend: Color gradient representing device count (1-32) - Model: Dashed black line - Annotations: 1. σ_CMO = 5 S/cm 2. F_CF = 11 nm **d) CMO Layer Defect Redistribution Graph** - Axes identical to section c - Legend: Same device count gradient - Model: Dashed black line - Annotations: 1. σ_CMO = 37 S/cm 2. F_CF = 11 nm (same as section c) ### Detailed Analysis **Structural Components (b)** - Total device thickness: 184nm (sum of all layers) - Conductive filament (CF) thickness: Not explicitly stated but implied as thin layer - Interface quality: Sharp boundaries between layers suggest controlled deposition **Electrical Characteristics (c-d)** 1. **Filament Radius Fit (c)** - Conductivity (σ_CMO): 5 S/cm - Critical filament radius (F_CF): 11 nm - Experimental data shows current saturation at ~3V - Model matches experimental trend with slight underestimation at low voltages 2. **Defect Redistribution (d)** - Conductivity (σ_CMO): 37 S/cm (7.4× improvement) - Same critical filament radius (F_CF): 11 nm - Experimental data shows higher current density across voltage range - Model follows same general trend but with better agreement at high voltages ### Key Observations 1. Conductivity improvement (σ_CMO) from 5→37 S/cm suggests effective defect engineering in CMO layer 2. Consistent F_CF (11 nm) across both graphs indicates stable filament formation mechanism 3. Experimental data shows device-to-device variability (color gradient) but maintains consistent trend 4. Model underestimates current at low voltages (<1V) but matches well at higher voltages (>2V) ### Interpretation The data demonstrates successful optimization of conductive filament formation through defect redistribution in the CMO layer. The 7.4× conductivity improvement while maintaining identical critical filament radius suggests: 1. Enhanced ionic mobility in HfOₓ interface layer 2. More uniform filament formation across devices 3. Improved reliability through controlled defect distribution The consistent F_CF value across both conditions indicates that the fundamental filament formation mechanism remains unchanged despite conductivity improvements. This suggests the optimization primarily affects interfacial properties rather than filament growth dynamics. The model's better agreement at high voltages implies that space-charge-limited conduction becomes dominant in the optimized device configuration. </details> Figure S1: ReRAM forming modelling. The CMO/HfO x ReRAM device is simulated using a 3D FEM in COMSOL Multiphysics 5.2 software. a The bird’s-eye view and b the lateral y-z view of the device’s geometry and material stack are shown. Due to the temperature and electric field confinement, an effective device area of 200 $\times$ 200 nm 2 is considered for the simulation to reduce computational resource demands. c The experimental array forming data in the low-voltage linear regime (from 0 to $0.2\,\mathrm{V}$ ) are fitted to extract the average filament radius. d The increase in experimental conductance resulting from a negative voltage sweep after the forming event is modelled as an effective increase in the electrical conductivity of the CMO layer, due to a radial redistribution of defects. <details> <summary>x8.png Details</summary>  ### Visual Description ## Multi-Subplot Analysis: Electronic Device Characterization ### Overview The image contains four subplots (a-d) depicting cumulative probability distributions and device characteristics for 1T1R (1 Transistor 1 Resistor) and ReRAM (Resistive Random-Access Memory) forming processes, along with triode resistance measurements. All plots use cumulative probability on the y-axis, with distinct x-axis parameters for each subplot. ### Components/Axes **Subplot a (1T1R Forming Voltage):** - **X-axis:** V_{1T1R forming} [V] (Voltage range: 2-4 V) - **Y-axis:** Cumulative Probability [%] - **Legend:** Dashed line = Mean (3.38 V) - **Data:** Blue circles (n=100+ data points) - **Key Feature:** Vertical dashed line at 3.38 V **Subplot b (1T1R Forming Current):** - **X-axis:** I_{1T1R forming} [μA] (Current range: 100-500 μA) - **Y-axis:** Cumulative Probability [%] - **Legend:** Dashed line = Mean (258 μA) - **Data:** Red circles (n=100+ data points) - **Key Feature:** Vertical dashed line at 258 μA **Subplot c (Triode Resistance):** - **X-axis:** V_DS [V] (Voltage range: 0-4 V) - **Y-axis:** I_DS [mA] (Current range: 0-0.8 mA) - **Legend:** - Black line = V_G = 1.2 V - Blue line = Triode characteristic - **Key Feature:** R_{triode DS} = 0.8 kΩ annotation **Subplot d (ReRAM Forming Voltage):** - **X-axis:** V_{ReRAM forming} [V] (Voltage range: 2-4 V) - **Y-axis:** Cumulative Probability [%] - **Legend:** Dashed line = Mean (3.17 V) - **Data:** Green circles (n=100+ data points) - **Key Feature:** Vertical dashed line at 3.17 V ### Detailed Analysis **Subplot a:** - Cumulative probability rises sharply from 20% to 95% between 3.0-3.5 V - Mean value (3.38 V) aligns with the steepest slope region - 95% probability achieved at ~3.8 V **Subplot b:** - Cumulative probability increases from 10% to 95% between 200-350 μA - Mean value (258 μA) corresponds to the inflection point - 95% probability reached at ~400 μA **Subplot c:** - Triode characteristic shows typical saturation behavior - Linear region (V_DS < 1 V) demonstrates ohmic behavior - Saturation region (V_DS > 2 V) shows near-constant current - R_{triode DS} = 0.8 kΩ calculated from linear region slope **Subplot d:** - Cumulative probability rises from 10% to 95% between 3.0-3.5 V - Mean value (3.17 V) matches the steepest slope region - 95% probability achieved at ~3.6 V ### Key Observations 1. All forming processes show similar sigmoidal cumulative distribution patterns 2. 1T1R forming voltage (3.38 V) and ReRAM forming voltage (3.17 V) are close but distinct 3. 1T1R forming current (258 μA) suggests current-controlled forming mechanism 4. Triode resistance (0.8 kΩ) indicates moderate channel conductance at V_G=1.2 V 5. All mean values fall within the steepest slope regions of their respective distributions ### Interpretation The data demonstrates: - **Device Thresholds:** The mean values represent critical forming thresholds for 1T1R and ReRAM devices - **Current-Voltage Relationship:** Subplot c reveals that 1T1R forming occurs at moderate V_DS where triode resistance is established - **Probability Distributions:** The similar shapes across subplots a, b, and d suggest comparable forming mechanisms despite different physical parameters - **Process Control:** The narrow probability distributions (95% within ~0.5 V/μA) indicate precise forming process control - **Material Properties:** The triode resistance measurement provides insight into channel quality and interface states The close proximity of 1T1R forming voltage (3.38 V) and ReRAM forming voltage (3.17 V) suggests potential for co-integration of these technologies, while the distinct current threshold (258 μA) highlights the importance of current control in 1T1R forming processes. </details> Figure S2: Experimental CMO/HfO x ReRAM array forming data. a The forming voltage distribution of the 1T1R cells within the array, defined as the voltage required to trigger the highest current increase during the quasi-static voltage sweep from 0 to $3.6\,\mathrm{V}$ in Fig. 2 a of the manuscript. b The array forming current distribution corresponding to $V=V_{\mathrm{forming}}^{\mathrm{1T1R}}$ . c The experimental resistance of the transistor in the triode region at $V_{\mathrm{G}}=\mathrm{1.2\,V}$ , extracted from a linear fit from 0 to $0.2\,\mathrm{V}$ of the transistor output characteristic. d The forming voltage distribution of the ReRAM array, shown in Fig. 2 c of the manuscript, computed as $V_{\mathrm{forming}}^{\mathrm{ReRAM}}$ = $V_{\mathrm{forming}}^{\mathrm{1T1R}}$ - $R_{\mathrm{DS}}^{\mathrm{triode}}$ * $I_{\mathrm{forming}}^{\mathrm{1T1R}}$ . <details> <summary>x9.png Details</summary>  ### Visual Description ## Line Chart: RESET: CMO Defect Depletion ### Overview The image depicts a logarithmic line chart illustrating the relationship between current (Current₁T1R) and voltage (Voltage₁T1R) during conductive metal oxide (CMO) defect depletion in a TiN/HfOₓ/TiN structure. Multiple colored lines represent different device configurations, with a color gradient indicating the number of devices (1–32). Two insets below the main graph show schematic diagrams of the material layers before and after defect depletion. --- ### Components/Axes - **Y-Axis (Left)**: - Label: `Current₁T1R [A]` - Scale: Logarithmic (10⁻⁹ to 10⁻³ A) - Position: Left side of the chart - **X-Axis (Bottom)**: - Label: `Voltage₁T1R [V]` - Scale: Linear (-1.5 V to 0.0 V) - Position: Bottom of the chart - **Color Bar (Right)**: - Label: `Devices` - Scale: 1 (purple) to 32 (yellow) - Position: Right side of the chart - **Insets (Bottom Center)**: - Two diagrams labeled `TiN`, `CMO`, and `HfOₓ` with white dots representing defects. - Left inset: CMO defects clustered in HfOₓ layer. - Right inset: CMO defects dispersed in TiN layer. --- ### Detailed Analysis 1. **Lines**: - **Trend**: All lines slope downward from the top-left (high current, low voltage) to the bottom-right (low current, high voltage), indicating current reduction as voltage increases. - **Color Gradient**: - Purple lines (1 device): Minimal current drop, suggesting fewer defects. - Yellow lines (32 devices): Steeper current drop, indicating higher initial defect density. - **Notable Features**: - Lines converge near the origin (0 V, 10⁻⁹ A), suggesting complete defect depletion at higher voltages. - Two circular annotations (① and ②) highlight specific voltage/current points. 2. **Insets**: - **Left Inset**: - CMO defects (white dots) concentrated in the HfOₓ layer between TiN electrodes. - Voltage polarity (`V_O`) indicated by arrows. - **Right Inset**: - CMO defects dispersed into the TiN layer, representing post-depletion state. --- ### Key Observations - **Defect Depletion Correlation**: Devices with higher initial defect density (yellow lines) exhibit steeper current-voltage curves, confirming that defect depletion reduces conductivity. - **Voltage Threshold**: All lines plateau near 0 V, implying a critical voltage range for effective defect migration. - **Material Layer Dynamics**: Insets suggest HfOₓ acts as a defect reservoir, while TiN facilitates defect migration. --- ### Interpretation The chart demonstrates that applying voltage (`V_O`) drives CMO defects from the HfOₓ layer into the TiN electrodes, reducing interfacial conductivity. The color-coded lines quantify this effect across 32 devices, showing that higher defect densities (yellow) require greater voltage to achieve depletion. The insets provide a physical model: HfOₓ initially traps defects, but voltage-induced electric fields redistribute them into TiN, altering the device’s resistive state. This aligns with resistive random-access memory (ReRAM) mechanisms, where defect migration modulates conductivity. **Critical Insight**: The convergence of lines at low current values suggests a universal depletion threshold, independent of initial defect density. This could inform optimization of ReRAM devices for consistent performance. </details> Figure S3: The experimental array’s response to the voltage sweep from 0 to $-1.5\,\mathrm{V}$ , following the positive forming and the initial negative voltage sweep (denoted as step (1) and (2) in Fig. 2 a of the manuscript, respectively). The oxygen vacancies in the CMO layer radially spread outward, depleting the CMO defect sub-band within a half-spherical volume at the interface with the conductive filament, leading to a reset process. <details> <summary>x10.png Details</summary>  ### Visual Description ## Line Graphs: Average T and E in the CMO Layer ### Overview The image contains two line graphs labeled **a** and **b**, depicting the relationship between voltage (V) and two physical properties in the CMO layer: - **Graph a**: Average temperature (T) in Kelvin (K). - **Graph b**: Average electric field (E) in volts per meter (V/m). Both graphs compare two datasets: **LRS** (Low Resistance State, red) and **HRS** (High Resistance State, blue). The x-axis spans voltage values from **-1.0 V to 0.9 V**, while the y-axes vary by property (temperature and electric field). --- ### Components/Axes #### Graph a (Temperature) - **X-axis**: Voltage [V], ranging from **-1.0 V to 0.9 V** in increments of 0.1 V. - **Y-axis**: Temperature [K], ranging from **293 K to 500 K** in increments of 50 K. - **Legend**: Located in the **top-right corner**, with: - **Red line**: LRS (Low Resistance State). - **Blue line**: HRS (High Resistance State). #### Graph b (Electric Field) - **X-axis**: Voltage [V], identical to Graph a. - **Y-axis**: Electric Field [V/m], logarithmic scale from **10⁷ to 10⁸ V/m** in increments of 10⁷ V/m. - **Legend**: Same as Graph a (top-right corner). --- ### Detailed Analysis #### Graph a (Temperature) - **LRS (Red Line)**: - Starts at **500 K** at **-1.0 V**. - Decreases sharply to **~293 K** at **0.0 V**. - Slightly increases to **~300 K** at **0.9 V**. - **HRS (Blue Line)**: - Remains flat at **~293 K** from **-1.0 V to 0.0 V**. - Rises sharply to **~350 K** at **0.9 V**. #### Graph b (Electric Field) - **LRS (Red Line)**: - Starts at **10⁸ V/m** at **-1.0 V**. - Drops sharply to **10⁷ V/m** at **0.0 V**. - Rises sharply to **10⁸ V/m** at **0.9 V** (V-shaped curve). - **HRS (Blue Line)**: - Remains flat at **10⁷ V/m** from **-1.0 V to 0.0 V**. - Rises sharply to **10⁸ V/m** at **0.9 V**. --- ### Key Observations 1. **Temperature Trends**: - LRS exhibits a **nonlinear response** to voltage, with a steep drop near 0 V followed by a minor increase. - HRS remains thermally stable until **0.9 V**, where it abruptly increases. 2. **Electric Field Trends**: - LRS shows a **V-shaped hysteresis**, with opposing electric field magnitudes at ±1.0 V and 0.9 V. - HRS demonstrates a **threshold behavior**, with no field until 0.9 V. 3. **Symmetry**: - Both graphs share identical voltage ranges and legend placement, suggesting a direct comparison of LRS/HRS behavior. --- ### Interpretation The data suggests that the CMO layer exhibits **distinct resistive and thermal responses** depending on its state (LRS vs. HRS): - **LRS**: - High initial temperature and electric field at negative voltages, dropping sharply at 0 V. This could indicate a phase transition or breakdown mechanism. - The V-shaped electric field implies **bipolar conduction** or domain wall motion under reverse bias. - **HRS**: - Thermal and electrical stability until a critical voltage (0.9 V), after which both properties surge. This may reflect a **threshold switching mechanism** common in resistive memory devices. The divergence in LRS/HRS behavior highlights the importance of material microstructure (e.g., grain boundaries, oxygen vacancies) in determining device performance. The logarithmic scale in Graph b emphasizes the **orders-of-magnitude difference** in electric field sensitivity between states. --- ### Notes on Data Extraction - All values are approximate, derived from visual interpolation of the plotted lines. - No textual data tables or additional categories are present. - Legends are consistently positioned in the **top-right corner** for both graphs. </details> Figure S4: The voltage-dependent evolution of a the average temperature and b electric field within a 3D half-spherical volume of the CMO layer situated atop the conductive filament in both HRS and LRS is presented. These trends serve as inputs for equation (6) of the manuscript. <details> <summary>x11.png Details</summary>  ### Visual Description ## Heatmap: CMO-HfOₓ ReRAM during programming ### Overview A heatmap visualizing the relationship between target conductance (μS) and cumulative distribution function (CDF) during ReRAM programming. Color intensity represents the number of states achieved, with a focus on an "Acceptance Range: 2% G_target". ### Components/Axes - **X-axis**: Target Conductance [μS] (10–90 μS, linear scale). - **Y-axis**: Cumulative Distribution Function (0.00–1.00, linear scale). - **Color Scale**: States (1–35, gradient from blue to red). - **Legend**: Located on the right; blue = low states, red = high states. - **Text Box**: "Acceptance Range: 2% G_target" in the top-left. ### Detailed Analysis - **Color Gradient**: - Blue (low states) dominates the left (10–30 μS). - Red (high states) dominates the right (70–90 μS). - Intermediate values (30–70 μS) show a gradient from light blue to orange. - **Acceptance Range**: - Defined as ±2% of G_target (e.g., for G_target = 50 μS, AR = ±1 μS). - Highlighted by the text box and implied by the heatmap’s color transitions. ### Key Observations - **Trend**: Higher target conductances correlate with higher state values (red regions). - **Outlier**: No explicit outliers; uniformity in color distribution within ranges. ### Interpretation The heatmap demonstrates that ReRAM programming success (measured by state count) increases with target conductance. The 2% acceptance range ensures minimal variability in conductance targeting, critical for reliable memory operation. --- ## Diagram: Flowchart of the closed-loop scheme ### Overview A flowchart detailing the adaptive programming process for ReRAM, including voltage selection, conductance measurement, and feedback loops. ### Components/Axes - **Decision Diamond**: "Measure G" with conditions: - G < G_target - AR → Apply SET pulse (V_set). - G > G_target + AR → Apply RESET pulse (V_reset). - **Voltage Boxes**: - **SET**: V_set = 1.35V (G_target ∈ [10,30] μS), V_reset = -1.5V. - **RESET**: V_set = 1.5V (G_target ∈ [60,90] μS), V_reset = -1.3V. - **Flow Direction**: Top-to-bottom, with arrows indicating process steps. ### Content Details 1. **Calculate acceptance range (AR) based on G_target**: - G_target ∈ [10,30] μS → AR = ±2% of G_target. - G_target ∈ [30,60] μS → AR = ±2% of G_target. - G_target ∈ [60,90] μS → AR = ±2% of G_target. 2. **Apply SET/RESET pulses**: - SET: V_set = 1.35V (low G_target), V_reset = -1.5V. - RESET: V_set = 1.5V (high G_target), V_reset = -1.3V. 3. **Write Success**: Achieved when G ∈ (G_target ± AR). ### Key Observations - **Conditional Logic**: Voltage selection depends on G_target’s range and measured conductance. - **Feedback Loop**: Continuous adjustment ensures G stays within the target ± AR. ### Interpretation The flowchart outlines an adaptive programming strategy where voltage pulses are dynamically adjusted based on real-time conductance measurements. This ensures precise targeting of G_target within a tight tolerance (2% AR), critical for stable ReRAM operation. The use of opposing voltages (SET/RESET) highlights the bidirectional control required for memory switching. </details> Figure S5: a The experimental cumulative distribution of conductance values for 35 representative programmed levels using 2% of G target as acceptance range. The closed-loop scheme based on identical pulses shown in Fig. 3 b of the manuscript and detailed in Methods is used. b Flowchart illustrating the identical-pulse closed-loop technique used for programming the ReRAM array into target analog conductance range. <details> <summary>x12.png Details</summary>  ### Visual Description ## Scatter Plots: I/O Quantization and IR Drop Analysis ### Overview Two scatter plots compare root mean square error (RMSE) against logarithmic time (Log(Time[s])) for different I/O quantization schemes and IR drop configurations. Chart **a** focuses on 64x64 configurations, while chart **b** examines scaling to 512x512. Both plots use logarithmic axes and include progression reference lines. --- ### Components/Axes #### Chart a: 64x64 Configurations - **X-axis**: Log(Time[s]) (0 to 20) - **Y-axis**: RMSE (10⁻³ to 10⁰) - **Legend**: - Green crosses: 64x64 IRdrop, 6/8bit I/O (Manuscript) - Blue squares: 64x64 IRdrop, 32/32bit I/O - Orange circles: 64x64 NO_IRdrop, 32/32bit I/O - **Dashed Lines**: - Green: "Prog." (RMSE ≈ 10⁻¹) - Blue: "Prog." (RMSE ≈ 10⁻²) - Orange: "Prog." (RMSE ≈ 10⁻³) #### Chart b: 512x512 Scaling - **X-axis**: Log(Time[s]) (0 to 20) - **Y-axis**: RMSE (10⁻² to 10⁰) - **Legend**: - Gray diamonds: 512x512 IRdrop, 6/8bit I/O - Green crosses: 64x64 IRdrop, 6/8bit I/O (Manuscript) - **Dashed Line**: - Gray: "Prog." (RMSE ≈ 10⁻¹) --- ### Detailed Analysis #### Chart a - **Green crosses (6/8bit I/O)**: - RMSE values: ~10⁻¹ to 10⁻² - Time range: 10⁻¹ to 10¹ seconds - **Blue squares (32/32bit I/O)**: - RMSE values: ~10⁻¹ - Time range: 10⁰ to 10¹ seconds - **Orange circles (NO_IRdrop)**: - RMSE values: ~10⁻¹ to 10⁰ - Time range: 10⁰ to 10¹ seconds - **Trends**: - Green crosses show the lowest RMSE, improving with time. - Blue squares and orange circles plateau at higher RMSE values. - Dashed lines indicate progression thresholds. #### Chart b - **Green crosses (64x64 6/8bit I/O)**: - RMSE values: ~10⁻¹ to 10⁻² - Time range: 10⁰ to 10¹ seconds - **Gray diamonds (512x512 6/8bit I/O)**: - RMSE values: ~10⁻¹ to 10⁰ - Time range: 10⁰ to 10¹ seconds - **Trends**: - Green crosses maintain lower RMSE than gray diamonds. - Progression line (10⁻¹) separates high and low performance. --- ### Key Observations 1. **IRdrop Impact**: Configurations with IRdrop (green crosses) consistently outperform NO_IRdrop (orange circles) in RMSE. 2. **Bit Depth Tradeoff**: 6/8bit I/O (green) achieves lower RMSE than 32/32bit I/O (blue/orange) at similar time scales. 3. **Scaling Effects**: 512x512 IRdrop (gray diamonds) shows higher RMSE than 64x64 IRdrop (green crosses), suggesting diminishing returns at larger scales. 4. **Progression Lines**: Dashed lines act as benchmarks, with performance clustering around or below these thresholds. --- ### Interpretation The data demonstrates that **IRdrop with lower bit I/O (6/8bit)** optimizes RMSE across both 64x64 and 512x512 scales, outperforming higher bit I/O (32/32bit) and configurations without IRdrop. The progression lines suggest that as time increases, systems with IRdrop approach or maintain performance near these benchmarks. Scaling to 512x512 introduces higher RMSE compared to 64x64, indicating potential architectural limitations at larger scales. The absence of IRdrop (orange circles) results in significantly worse performance, highlighting its critical role in error minimization. These findings align with the "Prog." thresholds, suggesting that IRdrop-enabled systems are designed to meet or exceed these targets. </details> Figure S6: The individual impact of IR-drop across array wires and input/output bit quantization on MVM accuracy. a Simulated RMSE compared to FP ideal results using 64x64 analog CMO/HfOx ReRAM array, shown as a function of the time after programming. Dashed horizontal lines represent the RMSE during programming, considering programming noise (with 0.2% G target as the acceptance range) but excluding relaxation effects. With 32-bit input/output quantization and no IR-drop (orange dots), an RMSE as low as 6 $10^{-3}$ is achieved during programming, which immediately increases (see the arrow) after relaxation (within $\mathrm{1\,s}$ ). Including the realistic IR-drop results in an overall RMSE increase (blue squares). Finally, reducing input/output quantization to 6/8 bits, respectively, leads to a further accuracy loss (green crosses), demonstrating that at short timescales (within 1 hour), the main analog MVM accuracy bottleneck is the reduced input/output quantization. After 1 hour, all cases converge, showing that the accuracy bottleneck is then dominated by the relaxation process. b By scaling up to a 512x512 array size (grey diamonds) and considering input/output quantization of 6/8 bits, IR-drop emerges as the primary bottleneck for analog MVM accuracy. <details> <summary>x13.png Details</summary>  ### Visual Description ## Chart/Diagram Type: Open-loop Pulsed Programming of CMO-HfO₂ ReRAM Array ### Overview The image displays 16 subplots arranged in a 4x4 grid, each illustrating conductance (G) measurements over pulse numbers during open-loop pulsed programming of a CMO-HfO₂ resistive random-access memory (ReRAM) array. Conductance is plotted on a logarithmic scale (10–100 μS), while pulse numbers range linearly from 0 to 2100. Each subplot includes three reference lines: G_min (blue dashed), G_max (red dashed), and G_sp (yellow dashed), with data points in blue and red. --- ### Components/Axes - **X-axis**: Pulse Number (0–2100, linear scale). - **Y-axis**: Conductance (G) in micro-siemens (μS), logarithmic scale (10–100 μS). - **Legend**: - G_min (blue dashed line): Minimum conductance threshold. - G_max (red dashed line): Maximum conductance threshold. - G_sp (yellow dashed line): Target/set-point conductance. - **Data Points**: - Blue: Low-conductance state (LRS). - Red: High-conductance state (HRS). --- ### Detailed Analysis 1. **Trends**: - All subplots show a biphasic conductance response: - **Rising Phase**: Conductance increases from ~10 μS (blue points) to ~100 μS (red points) as pulse numbers approach ~800–1600. - **Falling Phase**: Conductance drops sharply after ~1600 pulses, returning toward ~10 μS. - G_sp (yellow dashed line) consistently aligns with the peak conductance (~100 μS) in most subplots. - G_min and G_max lines bound the data points, with G_min (~10 μS) and G_max (~100 μS) representing the operational range. 2. **Data Points**: - Blue points (LRS) dominate the early and late pulse numbers. - Red points (HRS) cluster near the peak conductance (~100 μS) during the rising phase. - Variability in data point density suggests device-to-device or pulse-to-pulse noise. 3. **Axis Markers**: - X-axis ticks at 0, 800, 1600, 2100. - Y-axis ticks at 10, 100 μS. --- ### Key Observations - **Consistent Biphasic Behavior**: All subplots exhibit identical rising-falling conductance patterns, indicating reproducible switching dynamics. - **G_sp Alignment**: The yellow dashed line (G_sp) matches the peak conductance in most subplots, suggesting it represents a target state for programming. - **Device Variability**: Subtle differences in pulse-number thresholds for conductance transitions (e.g., ~800 vs. ~1200 pulses) may reflect device heterogeneity. - **Noise**: Scattered data points at low conductance (blue) indicate measurement uncertainty or stochastic switching. --- ### Interpretation This dataset demonstrates the open-loop pulsed programming of a CMO-HfO₂ ReRAM array, where conductance transitions between LRS and HRS are driven by repeated voltage pulses. The G_sp line likely represents the target conductance for a specific memory state (e.g., "1" in binary logic). The consistent biphasic response across subplots confirms the reproducibility of the switching mechanism, while variability in pulse-number thresholds highlights challenges in device uniformity. The logarithmic y-axis emphasizes the exponential nature of conductance changes during programming, critical for understanding ReRAM's non-volatile memory properties. Outliers in the falling phase (e.g., red points near G_min) may indicate incomplete switching or measurement artifacts. </details> Figure S7: The experimental response of the 8x4 CMO/HfO x ReRAM devices within the array to the open-loop programming pulse scheme (shown in Fig. 5 b of the manuscript) is shown. The set and reset pulse amplitudes are $1.35\,\mathrm{V}$ ( $V_{\mathrm{G}}=\mathrm{1.4\,V}$ ) and $-1.3\,\mathrm{V}$ ( $V_{\mathrm{G}}=\mathrm{3.3\,V}$ ), respectively, with a constant width of 2.5 µs due to setup limitations. <details> <summary>x14.png Details</summary>  ### Visual Description ## Line Graph: Generalized SBM vs SBM ### Overview The image is a line graph comparing experimental data (Exp. data) with two theoretical models: Generalized SBM (Gen SBM) and SBM. The graph plots "Normalized G" against "Pulse Number," showing oscillatory behavior with sharp transitions between positive and negative values. The experimental data is represented by red and blue circles, while the models are depicted as yellow and black lines. ### Components/Axes - **X-axis (Pulse Number)**: Ranges from 0 to 2100, with no intermediate labels. - **Y-axis (Normalized G)**: Ranges from -1 to 1, with gridlines at -1, 0, and 1. - **Legend**: Located in the top-right corner, with three entries: - **Exp. data**: Red and blue circles (open symbols). - **Gen SBM**: Yellow line. - **SBM**: Black line. ### Detailed Analysis 1. **Experimental Data (Exp. data)**: - Red circles cluster near the top of the graph (Normalized G ≈ 1) between Pulse Numbers 0–400 and 1200–1600. - Blue circles cluster near the bottom (Normalized G ≈ -1) between Pulse Numbers 400–800 and 1600–2100. - Data points are densely packed, with minimal scatter. 2. **Model Lines**: - **SBM (Black Line)**: - Follows the experimental data closely, with sharp transitions: - Rises from 0 to 1 between Pulse Numbers 0–400. - Drops to -1 between Pulse Numbers 400–800. - Rises to 1 between Pulse Numbers 800–1200. - Drops to -1 between Pulse Numbers 1200–1600. - Rises back to 0 between Pulse Numbers 1600–2100. - **Gen SBM (Yellow Line)**: - Mirrors the SBM line but with slightly smoother transitions, deviating minimally from the experimental data. 3. **Key Observations**: - Both models (SBM and Gen SBM) closely track the experimental data, suggesting high fidelity in capturing the underlying pattern. - The experimental data exhibits a binary-like oscillation, with abrupt shifts between positive and negative values. - The Gen SBM line (yellow) appears marginally smoother than the SBM line (black), but both align tightly with the data points. ### Interpretation The graph demonstrates that both the SBM and Gen SBM models effectively replicate the oscillatory behavior observed in the experimental data. The sharp transitions in the data suggest a system with binary or switch-like dynamics (e.g., on/off states). The close alignment between the models and the data implies that the generalized model (Gen SBM) does not significantly outperform the standard SBM in this context, though its smoother transitions might indicate a different underlying assumption or regularization. The experimental data’s tight clustering around the model lines highlights consistency in measurements, with no apparent outliers or anomalies. </details> Figure S8: The experimental open-loop pulsed response of a representative CMO/HfO x ReRAM device within the array shows that the potentiation and depression characteristics do not inherently saturate at the upper and lower boundaries. The generalized soft bounds model (yellow line) better captures this experimental trend compared to the saturated soft bounds model (black line). <details> <summary>x15.png Details</summary>  ### Visual Description ## Scatter Plots: Experimental vs. Generated SBM Data ### Overview Two scatter plots (G1 and G2) compare experimental array data (black dots) and generated stochastic block model (SBM) data (yellow diamonds). Both plots use the y-axis for "up_down" values, but differ in x-axis variables: G1 uses log-scaled "N_states" (10¹–10²), while G2 uses "γ" (0–3). Data points are spatially clustered, with experimental data showing tighter groupings than generated SBM. --- ### Components/Axes #### G1 (Left Plot) - **X-axis**: `N_states` (log scale, 10¹ to 10²) - **Y-axis**: `up_down` (-1.0 to 1.0) - **Legend**: - Black dots: "Exp. array data" - Yellow diamonds: "Gen. SBM" - **Spatial Grounding**: - Legend: Top-left corner - Data points: Scattered across the plot, with experimental data concentrated in the mid-range of `N_states` and `up_down`. #### G2 (Right Plot) - **X-axis**: `γ` (linear scale, 0.0 to 3.0) - **Y-axis**: `up_down` (-0.75 to 0.75) - **Legend**: - Black dots: "Exp. array data" - Yellow diamonds: "Gen. SBM" - **Spatial Grounding**: - Legend: Top-left corner - Data points: Experimental data clustered near `γ=1.5` and `up_down=0`, while generated SBM are more dispersed. --- ### Detailed Analysis #### G1 Trends - **Experimental Data (Black Dots)**: - Clustered between `N_states=10` and `N_states=50`, with `up_down` values ranging from -0.3 to 0.3. - No clear upward/downward trend; density decreases at extreme `N_states` values. - **Generated SBM (Yellow Diamonds)**: - Spread across the full `N_states` range (10¹–10²), with `up_down` values from -0.8 to 0.8. - Higher variability in both axes compared to experimental data. #### G2 Trends - **Experimental Data (Black Dots)**: - Concentrated near `γ=1.5` and `up_down=0`, forming a dense cluster. - Outliers extend to `γ=2.5` and `up_down=0.5`. - **Generated SBM (Yellow Diamonds)**: - Distributed across `γ=0.5–2.5` and `up_down=-0.7 to 0.7`. - Lower density near `γ=0` and `γ=3`, suggesting model limitations at extremes. --- ### Key Observations 1. **Experimental Data Clustering**: - In G1, experimental data are confined to mid-range `N_states` and moderate `up_down` values. - In G2, experimental data peak at `γ=1.5` with minimal `up_down` variation. 2. **Generated SBM Variability**: - Yellow diamonds in both plots show broader distributions, indicating higher stochasticity in modeled data. 3. **Axis Scale Impact**: - G1’s log-scaled `N_states` compresses high-value data, potentially obscuring trends at `N_states>50`. --- ### Interpretation - **Experimental vs. Model Behavior**: - Experimental data (black dots) exhibit tighter clustering, suggesting real-world constraints or stability in measured states. - Generated SBM (yellow diamonds) display greater variability, reflecting theoretical model flexibility or noise. - **γ Parameter Influence (G2)**: - The concentration of experimental data at `γ=1.5` may indicate an optimal or critical parameter value for the system under study. - **Outliers**: - Experimental data in G2 extend to `γ=2.5` and `up_down=0.5`, possibly representing edge cases or measurement artifacts. - **Log Scale Implications**: - G1’s log axis may underrepresent differences at high `N_states`, warranting caution in interpreting extreme values. This analysis highlights discrepancies between empirical measurements and theoretical models, emphasizing the need for validation across parameter spaces. </details> Figure S9: Multi-variate Gaussian distributions to reproduce the experimental inter-device variability. a Multi-variate gaussian G1 distribution of the experimental number of states and device asymmetry ( $up\_down$ ). b Gaussian G2 distribution of the analytical parameters $\gamma$ and $\gamma_{\rm up\_down}$ extracted from the generalized soft bounds model fitting to the experimental traces. ### Device modelling #### $up\_down$ parameter The $up\_down$ parameter is defined for the generalized soft bounds model in the simulation environment of the ‘aihwkit’ as the directional bias between the up and down update size ( $\Delta G^{+}$ and $\Delta G^{-}$ ). In addition, the minimum step in each direction d is described by the following expression [44]. $$ \displaystyle\Delta G^{d}=\Delta G_{SP}(1+d\beta+\sigma_{d-to-d}) \tag{7} $$ where d is -1 or 1 depending on the update direction. In contrast, the symmetry point is defined for each device as follows [23]: $$ \displaystyle SP=[\Delta G^{+}-\Delta G^{-}]/[\Delta G^{+}/(b_{\rm max}-\Delta G ^{+}/b_{\rm min})] \tag{8} $$ Where $\Delta G^{+}$ , $\Delta G^{-}$ define the minimum step size in the up and down direction respectively, and $b_{\rm max}$ and $b_{\rm min}$ represent the upper and lower bounds of the conductance. Therefore, considering an independent definition of each device (i.e. zero d-to-d variability) and a normalized conductance range between -1 and 1, the symmetry point device-level characteristic and the $up\_down$ analytical parameter are equivalent. #### Training setup For result replicability, the experimental parameters are incorporated into the simulation environment, where the Noise-to-Signal Ratio (NSR) is represented by ’dw_min_std’, normalized SP by ‘up_down’, normalized maximum and minimum conductances by ‘w_max’ and ‘w_min’ and min conductance step by ‘dw_min’. From this device model, analog training simulations were performed using AGAD considering a learning rate to update the weights of 1e-2, ‘fast_lr’ of 0.1 to update matrix, ‘transfer_every’ 3 iterations and batch size of 32. The FP baseline was obtained with SGD training using a learning rate of 1e-3 and batch size of 32.