2506.14138

# NeuroCoreX: An Open-Source FPGA-Based Spiking Neural Network Emulator with On-Chip Learning ††thanks: This manuscript has been authored in part by UT-Battelle, LLC under Contract No. DE-AC05-00OR22725 with the U.S. Department of Energy. The United States Government retains and the publisher, by accepting the article for publication, acknowledges that the United States Government retains a non-exclusive, paid-up, irrevocable, world-wide license to publish or reproduce the published form of this manuscript, or allow others to do so, for United States Government purposes. The Department of Energy will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (http://energy.gov/downloads/doe-public-access-plan).This material is based upon work supported by the U.S. Department of Energy, Office of Science, Office of Advanced Scientific Computing Research, under contract number DE-AC05-00OR22725. **Authors**: Ashish Gautam, Prasanna Date, Shruti Kulkarni, Robert Patton, Thomas Potok > Computer Science and Mathematics Division, Oak Ridge National Laboratory,Oak Ridge, Tennessee, USA.gautama@ornl.gov Abstract Spiking Neural Networks (SNNs) are computational models inspired by the structure and dynamics of biological neuronal networks. Their event-driven nature enables them to achieve high energy efficiency, particularly when deployed on neuromorphic hardware platforms. Unlike conventional Artificial Neural Networks (ANNs), which primarily rely on layered architectures, SNNs naturally support a wide range of connectivity patterns, from traditional layered structures to small-world graphs characterized by locally dense and globally sparse connections. In this work, we introduce NeuroCoreX, an FPGA-based emulator designed for the flexible co-design and testing of SNNs. NeuroCoreX supports all-to-all connectivity, providing the capability to implement diverse network topologies without architectural restrictions. It features a biologically motivated local learning mechanism based on Spike-Timing-Dependent Plasticity (STDP). The neuron model implemented within NeuroCoreX is the Leaky Integrate-and-Fire (LIF) model, with current-based synapses facilitating spike integration and transmission . A Universal Asynchronous Receiver-Transmitter (UART) interface is provided for programming and configuring the network parameters, including neuron, synapse, and learning rule settings. Users interact with the emulator through a simple Python-based interface, streamlining SNN deployment from model design to hardware execution. NeuroCoreX is released as an open-source framework, aiming to accelerate research and development in energy-efficient, biologically inspired computing. Index Terms: Neuromorphic computing, FPGA, STDP, Spiking Graph Neural Networks, Spiking Neural Networks, VHDL. I Introduction One of the primary goals of neuromorphic computing is to emulate the structure and dynamics of biological neuronal networks, achieving both brain-like energy efficiency and high computational accuracy. This is accomplished through the use of spiking neuron models implemented on neuromorphic chips. Over the past two decades, a variety of neuromorphic chips have been designed using both analog and digital ASIC platforms, capable of performing real-time information processing [13, 26, 27, 3, 28, 23]. However, the adoption of these systems remains constrained by their high cost, limited availability, and architectural specificity. Proprietary neuromorphic chips typically restrict user access and customization, creating significant barriers for researchers and students seeking to innovate and explore new designs. Field programmable gate arrays (FPGAs) offer a promising alternative, providing a flexible platform for prototyping and validating SNNs before final implementation on custom ASICs. They serve as an effective intermediate step, facilitating co-design development alongside off-the-shelf SNN simulators [8, 32]. Several digital ASICs and FPGA-based SNN systems have been proposed in the past [29, 22, 25]. While some proprietary systems [13] include local learning capabilities such as spike-timing-dependent plasticity (STDP), most FPGA-based implementations still rely heavily on offline training and lack real-time, on-chip learning. This limitation reduces their adaptability for dynamic, continuously evolving applications such as robotics, smart sensors, and edge computing. To address these challenges, we introduce NeuroCoreX, an open-source spiking neural network (SNN) emulator implemented in VHDL (Very High-Speed Integrated Circuit Hardware Description Language) for FPGA platforms. NeuroCoreX provides an affordable and flexible alternative for neuromorphic computing research and education. It is meant to be used in AI applications requiring low size, weight, and power (SWaP) such as edge computing, embedded systems, Internet of Things (IoT), and autonomous systems [30, 20, 1, 7, 6]. Unlike fixed-architecture hardware, it supports fully reconfigurable network topologies, from simple layered structures to complex small-world graphs. It incorporates biologically inspired local learning through a variant of the STDP learning rule [24], enabling on-chip, online adaptation of synaptic weights. The system uses a Leaky Integrate-and-Fire (LIF) neuron model with current-based synapses [19], ensuring both computational simplicity and biological relevance. This model of neuromorphic computation is known to be Turing-complete, i.e., capable of performing all the computations that a CPU/GPU can perform [12, 9]. As a result, NeuroCoreX can support not just SNN-based AI workloads but also general-purpose computing workloads [10, 11, 31, 34]. Programming and configuring NeuroCoreX is streamlined through a UART interface and a simple Python module, allowing users to modify network, neuron, synapse, and learning parameters easily. This makes NeuroCoreX not only a valuable research tool for testing new theories of learning and network organization but also a powerful educational platform for hands-on experience with neuromorphic hardware. Additionally, its energy-efficient architecture makes it well-suited for low-power AI applications in areas such as autonomous systems, smart sensors, and scientific instrumentation. The rest of the manuscript is organized as follows: Section II provides an overview and the architecture description of NeuroCoreX in detail. In Section III, we present the results demonstrating the functionality of the platform and evaluate its performance on the DIGITS dataset [2]. The manuscript concludes with a discussion of the results and planned future work in Section IV. II NeuroCoreX II-A NeuroCoreX overview NeuroCoreX is designed to emulate brain-like computation on reconfigurable FPGA hardware using a digital circuit approach. The system architecture is built around three fundamental components, inspired by biological neural networks: neurons, synapses, and a local learning mechanism. These elements are digitally realized in VHDL and operate together to support real-time, adaptive information processing. The neuron model employed is the LIF model, which captures the essential dynamics of biological neurons with computational efficiency and is known to be Turing-complete. Synapses are modeled with an exponential current response and store dynamic weight values that govern neuron-to-neuron influence. Learning is enabled through a simple variant of STDP, allowing synaptic strengths to evolve based on the relative timing of neuronal spikes. In its current implementation, NeuroCoreX supports networks of up to $N=100$ neurons with full all-to-all bidirectional connectivity using 10,000 synapses. In addition to recurrent connections, the system includes a separate set of 10,000 feedforward input synapses that serve as the interface for external stimuli. These input weights determine how incoming spikes—from sources such as sensors or preprocessed datasets—modulate the activity of neurons within the network. Neuronal dynamics are configured to emulate biological timescales. The network size and acceleration factor can be scaled depending on the memory resources of the FPGA, precision of the synaptic weights used and the operating clock frequency. Time-multiplexing and pipelining techniques are used to optimize hardware resource usage. A single physical neuron circuit is time-multiplexed to emulate the entire network. Communication with the FPGA is managed through a UART interface, with a Python module providing a user-friendly configuration and control interface. <details> <summary>extracted/6533360/images/NeuroCoreX_block_diagram.png Details</summary>  ### Visual Description ## System Diagram: FPGA-Based Spiking Neural Network ### Overview The image presents a system diagram of an FPGA-based spiking neural network (SNN) implementation. It illustrates the data flow and processing stages from the PC to the FPGA, including parameter loading, input data formatting, and output validation. The diagram also depicts the internal architecture of the FPGA, highlighting the LIF + STDP engine and memory structures. ### Components/Axes * **PC (Top-Left)**: Represents the host computer responsible for configuring the network and providing input data. * **1. Parameters for Neurons, synapses and initial weights**: Indicates the initial configuration data sent to the FPGA. * **2. Input Datasets Datasets Format**: Specifies the format of the input spike data. Spike time (8-bits), Neuron Address (16 bits). * **3. Output from FPGA Plot and validation**: Describes the output data used for validation. * **UART BUS (Center-Left)**: The communication interface between the PC and the FPGA. * **FPGA Artix 7 (Bottom-Right)**: The target hardware platform for the SNN implementation. * **Neuron & Synapse Parameters (Static) (Top-Center)**: Stores static parameters of the neurons and synapses. * **Weights (W_in) (Center)**: Stores the input weights. * **Weights (W_AA) (Top-Right)**: Stores the recurrent weights. * **LIF + STDP ENGINE (Center-Right)**: The core processing unit implementing the Leaky Integrate-and-Fire (LIF) neuron model and Spike-Timing-Dependent Plasticity (STDP) learning rule. * **FIFO I\_syn\_AA (Center-Right)**: FIFO memory for recurrent synaptic inputs. * "1 2 3 ... N" indicates the memory locations. * **FIFO I\_syn\_in (Center-Right)**: FIFO memory for input synaptic inputs. * "1 2 3 ... N" indicates the memory locations. * **FIFO Vmem (Center-Right)**: FIFO memory for neuron membrane potentials. * "1 2 3 ... N" indicates the memory locations. * **(a) (Bottom-Left)**: Overall system architecture. * **(b) (Bottom-Left)**: Network diagram showing input pixels connected to a recurrent layer. * **Image pixels (Left)**: Input layer representing image pixel values. * **W_in (Top-Center)**: Input weights connecting image pixels to the recurrent layer. * **W_AA (Center)**: Recurrent weights within the recurrent layer. * **(c) (Bottom-Right)**: Network diagram showing connections between neurons and topic outputs. * **W_in (Top-Left)**: Input weights. * **W_AA (Center)**: Recurrent weights. * **Topic 1 (Top-Right)**: Output representing topic 1. * **Topic 2 (Bottom-Right)**: Output representing topic 2. ### Detailed Analysis or ### Content Details * **Data Flow**: * Parameters for neurons, synapses, and initial weights are sent from the PC to the FPGA via the UART bus. * Input datasets, formatted as spike time (8-bits) and neuron address (16 bits), are sent from the PC to the FPGA via the UART bus. * Spike input data is stored in the Spike input FIFO. * The LIF + STDP engine processes the spike data and updates the weights (W_in and W_AA). * The updated weights (Delta\_w) are sent back to the Weights (W_in) and Weights (W_AA) blocks. * Output data from the FPGA is sent back to the PC for plotting and validation. * **Network Architecture**: * The network consists of an input layer (image pixels) connected to a recurrent layer. * The recurrent layer has recurrent connections (W_AA). * The recurrent layer is connected to topic outputs (Topic 1 and Topic 2). ### Key Observations * The system uses an FPGA to implement a spiking neural network. * The network uses LIF neurons and STDP learning. * The system includes FIFO memories for storing spike data and membrane potentials. * The network architecture includes an input layer, a recurrent layer, and topic outputs. ### Interpretation The diagram illustrates a hardware implementation of a spiking neural network on an FPGA. The system is designed to process spike data and learn using STDP. The network architecture is suitable for tasks such as image recognition and topic modeling. The use of an FPGA allows for parallel processing and real-time performance. The diagram provides a high-level overview of the system and its components. </details> Figure 1: (a). Block diagram of our FPGA based NeuroCoreX, (b). Feedforward SNN used for digits dataset classification, (c). Spiking Graph Neural Network for citation graph node classification problem. The operation of NeuroCoreX follows a structured emulation cycle (see Fig. 1 (a)). First, the network weights and initial configuration parameters for neuron, synapse, and learning rule are transferred from a PC to the FPGA via the UART interface. Once the network is set up, input spikes are streamed in real time, buffered in a First-In-First-Out (FIFO) module on the FPGA, and injected into the network precisely at their intended timestamps. At each neuron update cycle, the time-multiplexed processor sequentially updates the membrane potential, synaptic inputs, and firing status of each neuron. If a neuron fires, its effect on connected neurons is mediated through the all-to-all connected $W_{AA}$ weight matrix, and synaptic weights are updated in real time if STDP is enabled. Synaptic weights corresponding to feedforward inputs $W_{in}$ are similarly updated if STDP is enabled for them. The system thus continuously processes incoming spikes, updates network states, applies learning, and advances to the next time step, enabling real-time emulation of SNNs on the FPGA. Fig. 1 (a) shows a high-level block diagram of NeuroCoreX, along with two representative examples of network architectures that can be implemented on the FPGA. The first is a conventional feedforward SNN, a topology commonly used in neuromorphic research. We use this network to demonstrate digit classification on the well-known DIGITS dataset [2], showcasing NeuroCoreX’s support for standard inference tasks. The second network, shown in Fig. 1 (c), illustrates a SNN designed for node classification on citation graphs using STDP-based unsupervised learning. This architecture lacks a traditional layered structure and is instead defined by arbitrary, sparse connectivity encoded in the $W_{AA}$ matrix, which stores both plastic and static synaptic weights. These two examples highlight the flexibility of NeuroCoreX: in addition to supporting conventional layered architectures, the platform can implement non-layered networks such as those found in graph-based problems or generated via evolutionary algorithms like EONs . This versatility makes it suitable for a wide range of neuromorphic applications, from structured inference tasks to irregular and adaptive network topologies. II-B FPGA platform NeuroCoreX is implemented on the Artix-7 FPGA, a cost-effective and widely available platform that offers sufficient resources for neuromorphic prototyping. The system operates with a maximum internal clock frequency of 100 MHz. Two main clock domains are used: the high-frequency 100 MHz clock for UART-based communication and a 100 KHz lower-speed operating clock for neural processing. The combination of modest resource requirements, real-time adaptability, and biological plausibility makes the Artix-7 platform an ideal choice for NeuroCoreX. Scalability to larger networks or faster processing rates is primarily limited by the available block RAM and choice of clock frequency for neural processing on the FPGA. The UART interface operates at a baud rate of 1 Mbps, enabling efficient transmission and reception of both static configuration data and real-time input spikes. The FPGA receives network weights, neuron, synapse, and learning parameters from a host PC via this UART channel before execution begins. During operation, additional input spikes are streamed to the network in real time through the same interface. II-C Neuron and Synapse Models NeuroCoreX employs a biologically inspired computational model that integrates neuron dynamics, synaptic interactions, and local learning mechanisms. The neurons are modeled using a LIF formulation, adapted for efficient FPGA implementation. Each neuron has four configurable parameters, threshold, leak, refractory period, and reset voltage. The membrane potential V(t) is updated at each time step according to the following discrete-time equation: $$ V(t+1)=V(t)-\lambda+I_{\text{syn}}(t) $$ where $I_{\text{syn}}(t)$ is the total synaptic input current at timestep $t$ and $\lambda$ is the neuron’s leak. When the membrane potential exceeds the threshold $V_{\text{th}}$ , the neuron emits a spike, enters a refractory period $\tau_{\text{ref}}$ , and its membrane potential is reset to $V_{\text{reset}}$ . To ensure efficient real-time processing, all calculations are performed using a fixed-point format with 1 sign bit, 7 integer bits, and 10 fractional bits. Synaptic inputs are modeled as current-based exponential synapses, capturing biologically realistic, temporally decaying post-synaptic responses. The synaptic current dynamics follow the update rule: $$ I_{\text{syn}}(t+1)=I_{\text{syn}}(t)-\lambda_{\text{syn}} $$ where $\lambda_{\text{syn}}$ represents the synaptic current decay at each time step. Each synapse has an associated weight that determines its influence on the postsynaptic neuron. These synaptic weights, stored in BRAM, are dynamically updated during runtime. Weights are represented in signed 8-bit format, and appropriate resizing and bit-shifting are applied during computations to correctly integrate the synaptic current into the membrane potential. <details> <summary>extracted/6533360/images/Fig_2_RECT_STDP_inkscape.png Details</summary>  ### Visual Description ## Diagram: STDP Learning Rule and Matrix Representations ### Overview The image consists of two parts: (a) a graph illustrating the Spike-Timing-Dependent Plasticity (STDP) learning rule, showing the change in synaptic weight (Δw) as a function of the time difference (Δt) between pre- and post-synaptic spikes, and (b) a representation of matrices used in the model. ### Components/Axes **(a) STDP Learning Rule Graph:** * **X-axis:** Δt (ms), representing the time difference between post-synaptic and pre-synaptic spikes. The axis ranges from -45 ms to +45 ms, with marked values at -45, -30, -15, 0, 15, 30, and 45. The left side of the x-axis is labeled "tpost (ms)" and the right side is labeled "tpre (ms)". * **Y-axis:** Δw, representing the change in synaptic weight. The y-axis has values "+1 bit" and "-1 bit" marked. * **STDP Curve:** The curve shows that if the pre-synaptic spike occurs before the post-synaptic spike (Δt > 0), the synaptic weight increases (+1 bit) for Δt between 0 and 15 ms. If the post-synaptic spike occurs before the pre-synaptic spike (Δt < 0), the synaptic weight decreases (-1 bit) for Δt between -30 and 0 ms. **(b) Matrix Representations:** * **WAA:** A matrix representing synaptic weights, with elements w11, w12, ..., w1n, w21, w22, ..., w2n, ..., wn1, wn2, ..., wnn. * **synaptic_traces:** A matrix representing synaptic traces, with elements s11, s12, ..., s1n, s21, s22, ..., s2n, ..., sn1, sn2, ..., snn. * **update_state:** A matrix representing the update state, with elements u11, u12, ..., u1n, u21, u22, ..., u2n, ..., un1, un2, ..., unn. * **enable_STDP:** A matrix representing whether STDP is enabled, with elements e11, e12, ..., e1n, e21, e22, ..., e2n, ..., en1, en2, ..., enn. ### Detailed Analysis **(a) STDP Learning Rule Graph:** * For Δt between 0 and 15 ms, Δw = +1 bit. * For Δt between -30 and 0 ms, Δw = -1 bit. * For Δt < -30 ms and Δt > 15 ms, Δw = 0. **(b) Matrix Representations:** * Each matrix is an n x n matrix. * The elements of each matrix are denoted by their row and column indices. ### Key Observations * The STDP learning rule is a simplified model where synaptic weight changes are binary (+1 or -1 bit). * The matrices represent different aspects of a neural network model, including synaptic weights, synaptic traces, update states, and STDP enablement. ### Interpretation The STDP learning rule graph illustrates a fundamental principle of synaptic plasticity, where the timing of pre- and post-synaptic spikes determines the direction and magnitude of synaptic weight changes. The matrices in part (b) suggest a computational model of a neural network that incorporates STDP. The WAA matrix likely represents the current synaptic weights, while the synaptic_traces matrix may store information about recent pre- and post-synaptic activity. The update_state matrix could represent the changes to be applied to the synaptic weights, and the enable_STDP matrix could control whether STDP is active for specific synapses. The diagram provides a high-level overview of the components and processes involved in an STDP-based neural network model. </details> Figure 2: (a) Simplified STDP learning rule implemented on NeuroCoreX. (b) Internal variables stored in BRAM for tracking STDP updates. All matrices are of size $N× N$ and stored in row-major order. Each element of the $W_{AA}$ and synaptic_traces matrices is 8 bits wide, while update_state and enable_STDP are binary matrices. II-D Learning Rule NeuroCoreX implements a pair-based STDP rule using a rectangular learning window, a simplification widely demonstrated to maintain similar functional behavior to conventional exponential window [24] when the resolution of the weights is greater than 6-bits [17, 15, 5]. In this model (See Fig. 2 (a)), if a causal spike pair (presynaptic spike preceding postsynaptic spike) occurs within the window $t_{pre}$ , the synaptic weight is incremented by $dw_{pos}$ . If an acausal spike pair (postsynaptic spike preceding presynaptic spike) occurs, the weight is decremented by $dw_{neg}$ . $$ \Delta w=\begin{cases}dw_{\text{pos}},&\text{if}\quad 0<\Delta t<t_{\text{pre}% }\\ -dw_{\text{neg}},&\text{if}\quad 0<\Delta t<t_{\text{post}}\\ 0,&\text{otherwise}\end{cases} $$ Here, $\Delta t$ is the time difference between pre-and postsynaptic spikes, $dw_{\text{neg}}$ , $dw_{\text{pos}}$ , $t_{\text{pre}}$ , and $t_{\text{post}}$ are configurable parameters initialized via the Python-UART interface. The pre- and post-synaptic spike timings are tracked using dedicated time-trace registers stored in BRAM (see Fig. 2 (b)). These time traces are updated on each spike event and are used to detect causal or acausal spike pairings that trigger weight updates. For example, when neuron 1 spikes, all synaptic traces corresponding to its outgoing synapses are reset to zero, and the associated update_state entries are set to 1. In parallel, the post-synaptic trace (not shown in Fig. 2) is activated for all incoming synapses to neuron 1. At each subsequent time step, the active values in the synaptic trace matrices are incremented by 1. This process continues until the counter reaches $t_{\text{pre}}$ . If no other neuron spikes within this window, the trace value is reset to 0xFF (representing a negative disabled state), and the corresponding update_state entry is cleared. Similarly, if no neuron spiked within $t_{\text{post}}$ time steps prior to neuron 1’s spike, the post-synaptic trace is also reset to a negative value. However, if another neuron spikes within $t_{\text{pre}}$ time steps after neuron 1, the synaptic weight is incremented by $dw_{\text{pos}}$ , and both the synaptic trace and update_state for that synapse are reset. Conversely, if a neuron spiked within $t_{\text{post}}$ time steps prior to neuron 1, the synaptic weight is decremented by $dw_{\text{neg}}$ , and the associated trace and update_state values are reset. Thus, during each neuron update cycle, if a neuron spikes, the corresponding row and column addresses in the matrices shown in Fig. 2 (b) are accessed and updated. Based on the current states of these auxiliary matrices, the entries in the weight matrix $W_{AA}$ are modified accordingly. The enable_STDP matrix is a static binary mask configured via the Python interface at initialization. It acts as a filter to specify which synapses in $W_{AA}$ are subject to STDP-based plasticity. There a similar matrix for synapses in $W_{in}$ . II-E Network Architecture and System Operation The SNN architecture implemented on NeuroCoreX is illustrated in Fig. 1 (a). The network consists of upto $N=100$ LIF neurons instantiated on the FPGA. Two primary weight matrices define the network connectivity: $W_{AA}$ , a synaptic weight matrix for all-to-all, bidirectional connectivity between neurons in the FPGA and $W_{in}$ , a synaptic weight matrix for feedforward connections from external input sources to the neurons on the FPGA. Both matrices are stored in the FPGA’s BRAM. They can be initialized to user-defined values, and are accessed during SNN emulation. A synaptic weight value of zero indicates no connection between the corresponding neurons. Internal network dynamics are governed by the $W_{AA}$ matrix. This matrix allows every neuron to influence every other neuron bidirectionally. The matrix values determine the synaptic strengths between pairs of neurons and evolve over time via STDP-based learning. Both $W_{AA}$ and $W_{in}$ matrices support on-chip learning. To preserve network structure and prevent unwanted modifications, an associated binary filter matrix, called enable-STDP, is used for each weight matrix. If a weight’s corresponding enable-STDP entry is zero, the weight remains fixed throughout operation—even during learning phases. Weights representing nonexistent connections (zeros in the weight matrix) are thus protected from modification. In addition to the synaptic weights, the BRAMs are also used store the pre-and post synaptic traces necessary for STDP calculations. Weight matrices $W_{AA}$ and $W_{FF}$ , and the pre-and postsynaptic traces are stored as separate memory banks in row major order on the FPGA’s BRAM. As BRAM addresses must be accessed sequentially, the high-speed 100 MHz clock domain is utilized for reading, updating, and writing synaptic weights. During each clock cycle, synaptic weights and neuron states are updated in a pipelined manner to ensure efficient processing without data bottlenecks. NeuroCoreX utilizes time-multiplexing and pipelining techniques to emulate 100 neurons using a single physical neuron processing unit. Neuron updates are managed under a 100 kHz clock domain, such that updating all 100 neurons takes 1 millisecond, which closely matches the biological timescale of real neural systems. To accelerate the emulation, a higher update clock frequency can be used. For example, operating the neuron updates at 1 MHz results in a 10× speed-up relative to biological time for a network of 100 neurons. However, if the network size is increased to 1000 neurons while maintaining the 1 MHz clock, the full network would again require approximately 1 millisecond per time step, restoring biological equivalence. Thus, there exists a direct dependence between the number of neurons, the update clock frequency, and the effective emulated timescale. In the current implementation, the network size is limited to 100 neurons due to the available BRAM resources on the Artix-7 FPGA. Even with higher BRAM availability, the number of neurons that can be emulated is ultimately constrained by the difference between the clock frequency available for BRAM access and the clock rate used for updating the SNN states (see Section IV). Incoming spikes from external sources are transmitted via the UART interface. Each spike is encoded as a 24-bit word, comprising a 16-bit input neuron (or pixel) address and an 8-bit spike timing component. In the current implementation, the feedforward weight matrix $W_{\text{in}}$ is a $100× 100$ matrix, corresponding to 100 input neurons and 100 on-chip neurons. Although 8 bits are sufficient to encode the addresses of 100 input neurons, we chose to use 16 bits to provide flexibility for interfacing with larger sensor arrays. This allows the system to support up to 16K input neurons in future applications. In such cases, the feedforward matrix $W_{\text{in}}$ becomes a rectangular matrix of size $100× N_{\text{in}}$ , where $N_{\text{in}}$ denotes the number of input neurons in the external layer. For transmission efficiency, successive time differences between spikes are sent, rather than absolute times. These incoming spikes are temporarily stored in a FIFO buffer on the FPGA (See Fig. 1 (a)). The FIFO is designed to support simultaneous read and write operations, allowing it to continuously receive long temporal spike trains while concurrently feeding data to the network in real time without stalling. During network emulation, the system clock continuously increments an internal time counter. When the internal clock matches the timestamp of the spike at the FIFO head, the corresponding input neuron address is read. The associated weights from the $W_{in}$ matrix are then used to inject synaptic currents into the membrane potentials of the relevant neurons. If the synaptic current causes any neuron on the FPGA to spike, then associated weights from the $W_{AA}$ matrix are then read and used to inject synaptic currents into the membrane potentials of all other neurons connected to the spiking neuron in the network. III Results We present experimental results that demonstrate the usability, correctness, and flexibility of the NeuroCoreX platform across a range of SNN workloads. III-A Demonstrating User Interface Flexibility One of the key strengths of the NeuroCoreX platform lies in its flexible and intuitive user interface, which enables seamless communication between a host PC and the FPGA hardware through a Python-based control module. To demonstrate this capability, we highlight several core features supported by the interface. First, spike trains can be streamed from the PC to the FPGA for real-time emulation of spiking network activity. Figure 3 (b) shows a raster plot of spiking activity recorded during one such emulation run. Second, the user interface allows for real-time monitoring of internal neuron dynamics. Specifically, the membrane potential of any selected neuron can be captured and plotted as a time series, offering insight into subthreshold integration and spiking behavior. Figure 3 (a) shows the membrane potential trace of a representative neuron under input stimulation. The spike trains of all neurons and the membrane potential of a selected neuron are transferred back to the PC in real time. These signals are not stored on the FPGA. Instead, an internal FIFO module is used to buffer these signals, which allows for the continuous recording and visualization of network dynamics over long temporal duration without being limited by on-chip memory. Finally, the interface supports reading back synaptic weights from the FPGA after an STDP-enabled emulation. This feature enables direct inspection of weight evolution and verification of learning dynamics on hardware. It is particularly useful for comparing hardware learning outcomes with software simulations, facilitating debugging and model validation. These features collectively support efficient testing, inspection, and refinement of neuromorphic models, enabling a co-design loop between high-level model development and hardware validation. <details> <summary>extracted/6533360/images/Fig_3_PC_FPGA_UART.png Details</summary>  ### Visual Description ## Time Series and Spike Raster Plot ### Overview The image presents two plots. The top plot (a) shows a time series of a variable Vmem(au) over time, exhibiting a sawtooth pattern. The bottom plot (b) is a spike raster plot, displaying the spiking activity of 10 neurons over time. ### Components/Axes **Plot (a): Time Series** * **X-axis:** Time (s), ranging from 0.00 to 0.06, with tick marks at intervals of 0.01. * **Y-axis:** Vmem(au), ranging from 0 to 100, with tick marks at intervals of 20. * **Data:** A single blue line representing the time series data. **Plot (b): Spike Raster** * **Title:** FPGA Spike Raster * **X-axis:** Time (ms), ranging from 0 to 600, with tick marks at intervals of 100. * **Y-axis:** Neuron Index, ranging from 0 to 10, with tick marks at integer values. * **Data:** Blue vertical lines representing spikes for each neuron. ### Detailed Analysis **Plot (a): Time Series** * The blue line shows a repeating sawtooth pattern. The voltage increases linearly with time, followed by a sharp drop to near zero. * The period of the sawtooth wave is approximately 0.01 seconds. * The voltage rises from approximately 0 to approximately 100 au before dropping. **Plot (b): Spike Raster** * Each row represents a neuron, indexed from 1 to 10. * Each vertical blue line represents a spike event for that neuron at a specific time. * The spiking activity appears to be relatively consistent across the neurons, with some variations in the timing and frequency of spikes. * Neuron 4 appears to have a lower firing rate than the other neurons. ### Key Observations * The time series plot (a) shows a periodic charging and discharging behavior. * The spike raster plot (b) shows the timing of spikes for multiple neurons, revealing patterns of neural activity. ### Interpretation The time series plot likely represents the membrane potential of a neuron, where the linear increase corresponds to charging and the sharp drop corresponds to a spike event. The spike raster plot shows the activity of a population of neurons, potentially driven by the charging and discharging behavior observed in the time series plot. The FPGA Spike Raster title suggests this is a simulation or hardware implementation of a neural network. The consistent spiking activity across neurons suggests a synchronized or coordinated behavior within the network. Neuron 4's lower firing rate could indicate a different role or connectivity within the network. </details> Figure 3: (a) Membrane potential trace of a selected neuron, recorded from the FPGA during network emulation. (b) Spike raster plot showing activity of 10 neurons during a test run. Both plots were generated using data read back from the FPGA, demonstrating the observability and debugging capabilities of the NeuroCoreX interface. III-B DIGITS Dataset To verify the functional correctness of internal neuron and synapse computations on the FPGA, we performed inference on the DIGITS dataset [2] using a model trained in the SuperNeuroMAT simulator [8]. The dataset contains a total of 1,797 samples of handwritten digits, each represented as an $8× 8$ grayscale image with pixel values in the range $[0,15]$ . The dataset was split into 70% training samples and 30% test samples. A simple two-layer feedforward spiking neural network was trained using integrate-and-fire neurons and weighted synapses in the SuperNeuroMAT simulator. The input images were normalized to the range $[0,1]$ and converted into input spike trains using rate encoding. Each pixel intensity was encoded as twice the number of spikes and distributed uniformly over 32 time steps. During training, target labels were encoded by delivering a spike to the corresponding output neuron at timestep $t+1$ , one timestep after the input presentation at $t$ . The learning was carried out using one-shot STDP-based training. It is important to note that the training was not aimed at maximizing classification accuracy; rather, the goal was to validate the correctness of the internal neuron and synapse dynamics on the FPGA platform. Figure 4 shows the final weights of the output neurons after training, which clearly reflect the digit-specific patterns learned by the network. For deployment on NeuroCoreX, the trained weights and network parameters were transferred and initialized on the FPGA. The STDP learning rule was disabled during this phase to maintain fixed weights. The identical spike sequences for the test set were streamed to the FPGA through the UART interface. We achieved a test accuracy of 68% on the SuperNeuroMAT simulator, and the same accuracy was observed on the NeuroCoreX hardware. This result confirms that the FPGA implementation faithfully reproduces the dynamics of the simulated SNN and validates the correctness of internal spike integration, thresholding, and synaptic current accumulation in hardware. <details> <summary>x1.png Details</summary>  ### Visual Description ## Heatmap Grid: Digit Representation ### Overview The image presents a grid of heatmaps, each representing a digit from 0 to 9. The heatmaps visualize the distribution of some value (likely probability or frequency) across an 8x8 grid for each digit. A colorbar on the right indicates the mapping between color intensity and value. ### Components/Axes * **Heatmaps:** Ten individual heatmaps arranged in a 2x5 grid. Each heatmap represents a digit from 0 to 9. * **X-axis (each heatmap):** Ranges from 0 to 7, with a marker at 5. * **Y-axis (each heatmap):** Ranges from 0 to 7. * **Colorbar:** Vertical colorbar on the right side of the image, ranging from 0.000 to 0.014. The color gradient goes from black (0.000) to red to orange to yellow (0.014). * **Titles:** Each heatmap has a title indicating the digit it represents (0, 1, 2, 3, 4, 5, 6, 7, 8, 9). ### Detailed Analysis or ### Content Details **Heatmap Values and Trends:** * **Digit 0:** High values (yellow/orange) form a hollow oval shape. * **Digit 1:** High values are concentrated in a vertical line on the right side of the grid. * **Digit 2:** High values form a curve from the top-left to the bottom-right. * **Digit 3:** High values are concentrated in the upper-right and lower-right portions of the grid. * **Digit 4:** High values form a vertical line on the left and a horizontal line in the middle. * **Digit 5:** High values are concentrated in the upper-right and lower-left portions of the grid. * **Digit 6:** High values form a shape similar to '6', with a loop at the bottom. * **Digit 7:** High values are concentrated in the top-right portion of the grid, with a diagonal line extending downwards. * **Digit 8:** High values form two loops, one above the other. * **Digit 9:** High values form a shape similar to '9', with a loop at the top. **Colorbar Values:** * 0.000: Black * 0.002: Dark Red * 0.004: Red * 0.006: Orange-Red * 0.008: Orange * 0.010: Yellow-Orange * 0.012: Yellow * 0.014: Bright Yellow ### Key Observations * Each digit has a unique heatmap signature, reflecting the distribution of values across the grid. * The color intensity varies within each heatmap, indicating different levels of value concentration. * The heatmaps provide a visual representation of the features that distinguish each digit. ### Interpretation The heatmaps likely represent the average activation patterns of neurons in a neural network trained to recognize handwritten digits. The color intensity at each grid location indicates the importance or frequency of that pixel being activated when the corresponding digit is presented to the network. The distinct patterns for each digit suggest that the network has learned to extract unique features for each class. The values represent the probability or frequency of a pixel being activated for a given digit. </details> Figure 4: Heat-map of the trained weights from all the $10$ output neurons. III-C MicroSeer Dataset To evaluate the applicability of NeuroCoreX for graph-based learning tasks, we tested its performance using the MicroSeer dataset. MicroSeer is a reduced version of the Citeseer citation graph [4], containing 84 papers labeled with six topic categories. It was constructed by iteratively removing nodes from the largest connected component of Citeseer while ensuring that the resulting graph remained a single connected component. This connectivity was prioritized because it is assumed that learning from a very small, fragmented dataset would be ineffective. This reduction process yielded a total of 90 neurons, making the dataset well suited for deployment on NeuroCoreX, which supports up to 100 neurons and 10,000 bidirectional synapses. As compared to standard supervised learning that uses iterative error correction for weight updates, our training method leverages the graph’s structure directly to build the network. When testing a paper in the test data set, spiking the neuron associated with the test paper triggers a chain reaction of spikes. As these spikes travel between paper and topic neurons, STDP dynamically modifies the weights of the synapses connecting the test paper neuron to the topic neurons and vice versa. Subsequently, classification is achieved by finding the topic neuron with the highest final synaptic strength from the test paper neuron under consideration. The topic corresponding to this topic neuron is the one predicted by the SNN for the given test paper. The trained SNN model was first developed in the SuperNeuroMAT simulator and then ported to NeuroCoreX for hardware execution. When STDP was disabled, the network outputs from NeuroCoreX closely matched those produced by the simulator, demonstrating functional equivalence in inference. However, when STDP was enabled, a divergence in weight evolution and learning behavior was observed. This discrepancy stems from two primary sources: (1) SuperNeuro uses an exponential STDP learning rule with 64-bit floating-point precision, while NeuroCoreX implements a simplified rectangular learning window with signed 8-bit fixed-point weight representation; and (2) differences in numerical resolution and synaptic update timing result in non-identical learning trajectories. To achieve comparable accuracy metrics across simulation and hardware, tuning of learning parameters—such as learning rate, window size, and initial weight distributions—is required in both environments. These results underscore the importance of algorithm–hardware co-design in bridging the gap between simulation and deployment for neuromorphic graph learning. NeuroCoreX enables iterative testing and refinement of learning dynamics under realistic hardware constraints, facilitating the transition from simulated models to deployable systems. Future work will focus on tuning the system for MicroSeer and scaling to larger datasets on more advanced neuromorphic platforms. The total on-chip power consumption of the NeuroCoreX design was estimated at 305 mW, with 75% attributed to dynamic power. The Mixed-Mode Clock Manager (MMCM) accounted for the largest portion of dynamic power, followed by BRAMs, reflecting the memory-intensive nature of synaptic storage and buffering. IV Discussion and Conclusion NeuroCoreX enables real-time SNN emulation with STDP learning on low-cost FPGAs through a compact, open-source VHDL design. It bridges the gap between simulation and hardware by supporting seamless transfer of network models from SuperNeuroMAT, facilitating early-stage algorithm–hardware co-design under practical constraints like fixed-point precision and limited memory. Several key design choices in NeuroCoreX reflect critical trade-offs between biological realism, hardware efficiency, and scalability. IV-A Scalability One such decision is the use of an all-to-all connected network, which introduces significant memory overhead for weight storage—particularly as the network size increases. While this raises questions about scalability, the choice was made to provide maximum flexibility for users to implement arbitrary network architectures, and it is essential for supporting densely connected networks. An alternative approach would be to store a list of addresses corresponding to either all outgoing or incoming neurons for each neuron. This is more efficient for sparsely connected networks, as it avoids storing unnecessary weights. However, it becomes highly inefficient for densely connected networks, as it requires additional BRAM to store connection addresses alongside the weights. Since real-world networks often include a mix of dense and sparse connectivity, a scalable solution should combine both approaches. In such a hybrid model, densely connected sub-networks can be mapped directly onto NeuroCoreX’s all-to-all weight matrix, while sparse connections between these sub-networks can be implemented across multiple physical instances of NeuroCoreX. Each instance would represent a densely connected region of the larger network. With this strategy, the NeuroCoreX platform can be scaled effectively to support larger, more biologically realistic networks. We plan to implement this hybrid approach in future iterations of NeuroCoreX. IV-B Scalability and Network Acceleration Trade-offs NeuroCoreX employs time-multiplexing to emulate 100 virtual neurons using a single physical processing unit, significantly reducing hardware resource usage. However, this approach introduces a fundamental trade-off between the number of neurons that can be emulated, the achievable acceleration timescale, and the clock frequency used. Increasing the number of virtual neurons directly increases the time required to complete a single simulation step unless the update clock is proportionally scaled. In the Artix-7 FPGA used for this work, the 100-neuron configuration utilizes nearly the full BRAM capacity due to storage requirements for a) the FIFO buffer that stores and transmits input spike trains to the network in real time, b) FIFO to store membrane potential, and synaptic current for the time multiplexed implementation, c) FIFO to transmit spike trains of all neurons back to PC, d) synaptic weight matrices $W_{AA}$ and $W_{in}$ , e) the update and enable-STDP masks, and f) the pre- and post-synaptic trace registers required for learning. Even with more memory on higher-end FPGAs, scalability is constrained by the interaction between memory bandwidth and update clock frequency. BRAM access is sequential, with only one read or write per port per cycle, creating a bottleneck during real-time weight updates. For biologically realistic timing, the memory clock must run significantly faster than the neuron update clock. In our system, BRAM is accessed at 100 MHz while neuron updates proceed at 100 kHz, enabling a 1000 $×$ speedup. Assuming BRAM size is not a limiting factor, the theoretical upper bound for network size under this configuration is approximately 500 neurons. This limit arises from the need for up to 500 cycles each for STDP potentiation and depression, which cannot occur concurrently on the same matrix. Beyond this, the system cannot complete all required memory operations within a single time step unless either the clock domains are further decoupled or memory bandwidth is increased. These constraints underscore a core design trade-off between network size, update speed, and biological fidelity. Depending on the target application, designers must balance these factors—favoring high-throughput inference, real-time learning, or alignment with biologically realistic timescales. IV-C Applications The flexibility, low cost, and on-chip learning capabilities of NeuroCoreX make it well suited for edge AI applications such as robotics, neuromorphic sensing, and adaptive control. Its energy-efficient architecture supports real-time inference and learning without reliance on offline processing. In educational settings, NeuroCoreX offers a unique platform for students to bridge the gap between software simulation and digital hardware design. By working directly with spiking neuron models and real-time hardware behavior, students gain hands-on experience with both computational neuroscience concepts and hardware engineering practices. As an open-source framework, NeuroCoreX also encourages community-driven extensions, reproducibility of results, and transparent benchmarking of neuromorphic algorithms under realistic hardware constraints. Several FPGA-based neuromorphic hardware platforms have been reported in the literature [33], each targeting different performance and application trade-offs. Caspian [29], for instance, has been widely used in edge applications involving control and classification tasks [30]. It supports configurable, though limited, connectivity and can be deployed on low-cost FPGAs. Liu et al. [22] proposed NHAP, a platform optimized for high-speed and low-power execution of SNNs, supporting multiple neuron models on mid- to high-end FPGAs. Matinizadeh et al. [25] introduced SONIC, an end-to-end framework for neuromorphic computing on FPGAs, which includes a core SNN engine called QUANTISENC, written in VHDL. This framework demonstrates several classification and control applications using fixed-topology layered networks. None of the existing FPGA-based neuromorphic platforms offer the full set of features provided by NeuroCoreX—most notably, on-chip learning via STDP. While some focus on high-speed inference or limited configurability, they typically lack embedded learning and depend on offline training. Most also lack a fully open-source toolchain, limiting their adoption in research and education. In contrast, NeuroCoreX combines real-time operation, on-chip STDP, flexible connectivity, and open-source support, making it a unique platform for deployment and algorithm–hardware co-design. IV-D Future Work Future enhancements to NeuroCoreX will focus on improving scalability and runtime efficiency. To support faster synaptic updates during STDP, we plan to explore multi-port BRAM architectures [21], which can alleviate memory bandwidth limitations by allowing concurrent read and write access to synaptic data. The modular design of NeuroCoreX also allows for replacing the current LIF neuron model with more biologically plausible alternatives [16, 19], enabling broader exploration of neural dynamics in hardware. Higher-order STDP rules, such as triplet-based [18] and neuromodulated STDP [14], have shown comparable learning performance to conventional STDP while requiring as little as 3-bit fixed-point resolution per synapse. Integrating these models may slightly increase logic complexity but could significantly reduce BRAM usage, enabling simulation of larger networks. Additionally, exposing pipeline depth and clock parameters as configurable settings would allow fine-tuning for task-specific trade-offs between performance and biological fidelity. NeuroCoreX provides an efficient, accessible, and extensible platform for implementing biologically inspired, energy-efficient SNNs on FPGA hardware. With its modular VHDL design, real-time STDP learning, and flexible connectivity, it enables researchers and educators to explore neuromorphic principles under realistic hardware constraints. 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